summaryrefslogtreecommitdiff
path: root/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/pwrseq.h
blob: 36b3e91d996e96c59b91fb9bb759beb36a94d164 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
/******************************************************************************
 *
 * Copyright(c) 2009-2010  Realtek Corporation.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of version 2 of the GNU General Public License as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * The full GNU General Public License is included in this distribution in the
 * file called LICENSE.
 *
 * Contact Information:
 * wlanfae <wlanfae@realtek.com>
 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
 * Hsinchu 300, Taiwan.
 *
 * Larry Finger <Larry.Finger@lwfinger.net>
 *
 *****************************************************************************/

#ifndef __RTL8821AE_PWRSEQ_H__
#define __RTL8821AE_PWRSEQ_H__

#include "../pwrseqcmd.h"
#include "../btcoexist/halbt_precomp.h"

#define	RTL8812_TRANS_CARDEMU_TO_ACT_STEPS	15
#define	RTL8812_TRANS_ACT_TO_CARDEMU_STEPS	15
#define	RTL8812_TRANS_CARDEMU_TO_SUS_STEPS	15
#define	RTL8812_TRANS_SUS_TO_CARDEMU_STEPS	15
#define	RTL8812_TRANS_CARDEMU_TO_PDN_STEPS	25
#define	RTL8812_TRANS_PDN_TO_CARDEMU_STEPS	15
#define	RTL8812_TRANS_ACT_TO_LPS_STEPS		15
#define	RTL8812_TRANS_LPS_TO_ACT_STEPS		15
#define	RTL8812_TRANS_END_STEPS			1

/* The following macros have the following format:
 * { offset, cut_msk, fab_msk|interface_msk, base|cmd, msk, value
 *   comments },
 */
#define RTL8812_TRANS_CARDEMU_TO_ACT					\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
	/* disable SW LPS 0x04[10]=0*/},	\
	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \
	/* wait till 0x04[17] = 1    power ready*/},	\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
	/* disable HWPDN 0x04[15]=0*/}, \
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
	/* disable WL suspend*/},	\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
	/* polling until return 0*/},	\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},

#define RTL8812_TRANS_ACT_TO_CARDEMU													\
	{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \
	 /* 0xc00[7:0] = 4	turn off 3-wire */},	\
	{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \
	 /* 0xe00[7:0] = 4	turn off 3-wire */},	\
	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
	 /* 0x2[0] = 0	 RESET BB, CLOSE RF */},	\
	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US \
	/*Delay 1us*/},	\
	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
	  /* Whole BB is reset*/},			\
	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x2A \
	 /* 0x07[7:0] = 0x28 sps pwm mode 0x2a for BT coex*/},	\
	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0 \
	/*0x8[1] = 0 ANA clk =500k */},	\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
	 /*0x04[9] = 1 turn off MAC by HW state machine*/},	\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0 \
	 /*wait till 0x04[9] = 0 polling until return 0 to disable*/},

#define RTL8812_TRANS_CARDEMU_TO_SUS					\
	{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xc0}, \
	{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xE0}, \
	{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07 \
	/* gpio11 input mode, gpio10~8 output mode */},	\
	{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
	/* gpio 0~7 output same value as input ?? */},	\
	{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff \
	/* gpio0~7 output mode */},	\
	{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
	/* 0x47[7:0] = 00 gpio mode */},	\
	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
	/* suspend option all off */},	\
	{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7 \
	/*0x14[7] = 1 turn on ZCD */},	\
	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
	/* 0x15[0] =1 trun on ZCD */},	\
	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \
	/*0x23[4] = 1 hpon LDO sleep mode */},	\
	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0 \
	/*0x8[1] = 0 ANA clk =500k */},	\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \
	/*0x04[11] = 2b'11 enable WL suspend for PCIe*/},

#define RTL8812_TRANS_SUS_TO_CARDEMU					\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
	/*0x04[11] = 2b'01enable WL suspend*/},   \
	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0 \
	/*0x23[4] = 0 hpon LDO sleep mode leave */},	\
	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0 \
	/* 0x15[0] =0 trun off ZCD */},	\
	{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0 \
	/*0x14[7] = 0 turn off ZCD */},	\
	{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
	/* gpio0~7 input mode */},	\
	{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
	/* gpio11 input mode, gpio10~8 input mode */},

#define RTL8812_TRANS_CARDEMU_TO_CARDDIS				\
	{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
	/*0x03[2] = 0, reset 8051*/},	\
	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x05 \
	/*0x80=05h if reload fw, fill the default value of host_CPU handshake field*/},	\
	{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xcc}, \
	{0x0042, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xF0, 0xEC}, \
	{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x07 \
	/* gpio11 input mode, gpio10~8 output mode */},	\
	{0x0045, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
	/* gpio 0~7 output same value as input ?? */},	\
	{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xff \
	/* gpio0~7 output mode */},	\
	{0x0047, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
	/* 0x47[7:0] = 00 gpio mode */},	\
	{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7 \
	/*0x14[7] = 1 turn on ZCD */},	\
	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
	/* 0x15[0] =1 trun on ZCD */},	\
	{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0 \
	/*0x12[0] = 0 force PFM mode */},	\
	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \
	/*0x23[4] = 1 hpon LDO sleep mode */},	\
	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x02, 0 \
	/*0x8[1] = 0 ANA clk =500k */},	\
	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \
	 /*0x07=0x20 , SOP option to disable BG/MB*/},	\
	{0x001f, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
	 /*0x01f[1]=0 , disable RFC_0  control  REG_RF_CTRL_8812 */},	\
	{0x0076, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
	 /*0x076[1]=0 , disable RFC_1  control REG_OPT_CTRL_8812 +2 */},	\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, BIT3 \
	 /*0x04[11] = 2b'01 enable WL suspend*/},

#define RTL8812_TRANS_CARDDIS_TO_CARDEMU				\
	{0x0012, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
	/*0x12[0] = 1 force PWM mode */},	\
	{0x0014, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, 0 \
	/*0x14[7] = 0 turn off ZCD */},	\
	{0x0015, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, 0 \
	/* 0x15[0] =0 trun off ZCD */},	\
	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, 0 \
	/*0x23[4] = 0 hpon LDO leave sleep mode */},	\
	{0x0046, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
	/* gpio0~7 input mode */},	\
	{0x0043, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
	/* gpio11 input mode, gpio10~8 input mode */}, \
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \
	 /*0x04[10] = 0, enable SW LPS PCIE only*/},	\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3, 0 \
	 /*0x04[11] = 2b'01enable WL suspend*/},	\
	{0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \
	 /*0x03[2] = 1, enable 8051*/},	\
	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
	/*PCIe DMA start*/},

#define RTL8812_TRANS_CARDEMU_TO_PDN		\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7 \
	/* 0x04[15] = 1*/},

#define RTL8812_TRANS_PDN_TO_CARDEMU			\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
	/* 0x04[15] = 0*/},

#define RTL8812_TRANS_ACT_TO_LPS		\
	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
	/*PCIe DMA stop*/},	\
	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x7F \
	/*Tx Pause*/},		\
	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
	/*Should be zero if no packet is transmitting*/},	\
	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
	/*Should be zero if no packet is transmitting*/},	\
	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
	/*Should be zero if no packet is transmitting*/},	\
	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
	/*Should be zero if no packet is transmitting*/},	\
	{0x0c00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \
	 /* 0xc00[7:0] = 4	turn off 3-wire */},	\
	{0x0e00, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x04 \
	 /* 0xe00[7:0] = 4	turn off 3-wire */},	\
	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
	/*CCK and OFDM are disabled,and clock are gated,and RF closed*/},	\
	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US \
	/*Delay 1us*/},	\
	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
	  /* Whole BB is reset*/},			\
	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03 \
	/*Reset MAC TRX*/},			\
	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
	/*check if removed later*/},		\
	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
	/*Respond TxOK to scheduler*/},

#define RTL8812_TRANS_LPS_TO_ACT					\
	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
	PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84 \
	 /*SDIO RPWM*/},	\
	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
	 /*USB RPWM*/},	\
	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
	 /*PCIe RPWM*/},	\
	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS \
	 /*Delay*/},	\
	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
	 /*.	0x08[4] = 0		 switch TSF to 40M*/},	\
	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0 \
	 /*Polling 0x109[7]=0  TSF in 40M*/},			\
	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
	 /*.	0x29[7:6] = 2b'00	 enable BB clock*/},	\
	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
	 /*.	0x101[1] = 1*/},					\
	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
	 /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/},	\
	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
	 /*.	0x02[1:0] = 2b'11	 enable BB macro*/},	\
	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
	 /*.	0x522 = 0*/},

#define RTL8812_TRANS_END					\
	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
	0, PWR_CMD_END, 0, 0},

extern struct wlan_pwr_cfg  rtl8812_power_on_flow
		[RTL8812_TRANS_CARDEMU_TO_ACT_STEPS +
		 RTL8812_TRANS_END_STEPS];
extern struct wlan_pwr_cfg  rtl8812_radio_off_flow
		[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
		 RTL8812_TRANS_END_STEPS];
extern struct wlan_pwr_cfg  rtl8812_card_disable_flow
		[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
		 RTL8812_TRANS_CARDEMU_TO_PDN_STEPS +
		 RTL8812_TRANS_END_STEPS];
extern struct wlan_pwr_cfg  rtl8812_card_enable_flow
		[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
		 RTL8812_TRANS_CARDEMU_TO_PDN_STEPS +
		 RTL8812_TRANS_END_STEPS];
extern struct wlan_pwr_cfg  rtl8812_suspend_flow
		[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
		 RTL8812_TRANS_CARDEMU_TO_SUS_STEPS +
		 RTL8812_TRANS_END_STEPS];
extern struct wlan_pwr_cfg  rtl8812_resume_flow
		[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
		 RTL8812_TRANS_CARDEMU_TO_SUS_STEPS +
		 RTL8812_TRANS_END_STEPS];
extern struct wlan_pwr_cfg  rtl8812_hwpdn_flow
		[RTL8812_TRANS_ACT_TO_CARDEMU_STEPS +
		 RTL8812_TRANS_CARDEMU_TO_PDN_STEPS +
		 RTL8812_TRANS_END_STEPS];
extern struct wlan_pwr_cfg  rtl8812_enter_lps_flow
		[RTL8812_TRANS_ACT_TO_LPS_STEPS +
		 RTL8812_TRANS_END_STEPS];
extern struct wlan_pwr_cfg  rtl8812_leave_lps_flow
		[RTL8812_TRANS_LPS_TO_ACT_STEPS +
		 RTL8812_TRANS_END_STEPS];

/* Check document WM-20130516-JackieLau-RTL8821A_Power_Architecture-R10.vsd
 *	There are 6 HW Power States:
 *	0: POFF--Power Off
 *	1: PDN--Power Down
 *	2: CARDEMU--Card Emulation
 *	3: ACT--Active Mode
 *	4: LPS--Low Power State
 *	5: SUS--Suspend
 *
 *	The transision from different states are defined below
 *	TRANS_CARDEMU_TO_ACT
 *	TRANS_ACT_TO_CARDEMU
 *	TRANS_CARDEMU_TO_SUS
 *	TRANS_SUS_TO_CARDEMU
 *	TRANS_CARDEMU_TO_PDN
 *	TRANS_ACT_TO_LPS
 *	TRANS_LPS_TO_ACT
 *
 *	TRANS_END
 */
#define	RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS	25
#define	RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS	15
#define	RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS	15
#define	RTL8821A_TRANS_SUS_TO_CARDEMU_STEPS	15
#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU_STEPS	15
#define	RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS	15
#define	RTL8821A_TRANS_PDN_TO_CARDEMU_STEPS	15
#define	RTL8821A_TRANS_ACT_TO_LPS_STEPS		15
#define	RTL8821A_TRANS_LPS_TO_ACT_STEPS		15
#define	RTL8821A_TRANS_END_STEPS		1

#define RTL8821A_TRANS_CARDEMU_TO_ACT					\
	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,			\
	 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
	 /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/},   \
	{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,		\
	 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
	 /*0x67[0] = 0 to disable BT_GPS_SEL pins*/},	\
	{0x0001, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,			\
	 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_DELAY, 1, PWRSEQ_DELAY_MS \
	/*Delay 1ms*/},   \
	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,			\
	 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, 0 \
	 /*0x00[5] = 1b'0 release analog Ips to digital ,1:isolation*/},   \
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0 \
	/* disable SW LPS 0x04[10]=0 and WLSUS_EN 0x04[12:11]=0*/},	\
	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , BIT0 \
	/* Disable USB suspend */},	\
	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \
	/* wait till 0x04[17] = 1    power ready*/},	\
	{0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0 , 0 \
	/* Enable USB suspend */},	\
	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
	/* release WLON reset  0x04[16]=1*/},	\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
	/* disable HWPDN 0x04[15]=0*/},	\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0 \
	/* disable WL suspend*/},	\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
	/* polling until return 0*/},	\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0 \
	/**/},	\
	{0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
	/*0x4C[24] = 0x4F[0] = 1, switch DPDT_SEL_P output from WL BB */},\
	{0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4) \
	/*0x66[13] = 0x67[5] = 1, switch for PAPE_G/PAPE_A 	\
	 from WL BB ; 0x66[12] = 0x67[4] = 1, switch LNAON from WL BB */},\
	{0x0025, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6, 0 \
	/*anapar_mac<118> , 0x25[6]=0 by wlan single function*/},\
	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
	/*Enable falling edge triggering interrupt*/},\
	{0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
	/*Enable GPIO9 interrupt mode*/},\
	{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
	/*Enable GPIO9 input mode*/},\
	{0x0058, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
	/*Enable HSISR GPIO[C:0] interrupt*/},\
	{0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
	/*Enable HSISR GPIO9 interrupt*/},\
	{0x007A, PWR_CUT_TESTCHIP_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3A \
	/*0x7A = 0x3A start BT*/},\
	{0x002E, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF , 0x82  \
	/* 0x2C[23:12]=0x820 ; XTAL trim */}, \
	{0x0010, PWR_CUT_A_MSK , PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6 , BIT6  \
	/* 0x10[6]=1  */},

#define RTL8821A_TRANS_ACT_TO_CARDEMU					\
	{0x001F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
	/*0x1F[7:0] = 0 turn off RF*/},	\
	{0x004F, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
	/*0x4C[24] = 0x4F[0] = 0, switch DPDT_SEL_P output from		\
	 register 0x65[2] */},\
	{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
	/*Enable rising edge triggering interrupt*/}, \
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
	 /*0x04[9] = 1 turn off MAC by HW state machine*/},	\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0 \
	 /*wait till 0x04[9] = 0 polling until return 0 to disable*/},	\
	{0x0000, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,			\
	 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
	 /*0x00[5] = 1b'1 analog Ips to digital ,1:isolation*/},   \
	{0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,		\
	 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
	 /*0x20[0] = 1b'0 disable LDOA12 MACRO block*/},

#define RTL8821A_TRANS_CARDEMU_TO_SUS					\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3) \
	 /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/},	\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,		\
	 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \
	 /*0x04[12:11] = 2b'01 enable WL suspend*/},	\
	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
	 /*0x23[4] = 1b'1 12H LDO enter sleep mode*/},   \
	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \
	 /*0x07[7:0] = 0x20 SDIO SOP option to disable BG/MB/ACK/SWR*/},   \
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4 \
	 /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/},	\
	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
	PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0 \
	 /*Set SDIO suspend local register*/},	\
	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
	PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0 \
	 /*wait power state to suspend*/},

#define RTL8821A_TRANS_SUS_TO_CARDEMU					\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0 \
	 /*clear suspend enable and power down enable*/},	\
	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
	PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0 \
	 /*Set SDIO suspend local register*/},	\
	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
	PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1 \
	 /*wait power state to suspend*/},\
	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
	 /*0x23[4] = 1b'0 12H LDO enter normal mode*/},   \
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \
	 /*0x04[12:11] = 2b'01enable WL suspend*/},

#define RTL8821A_TRANS_CARDEMU_TO_CARDDIS				\
	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \
	 /*0x07=0x20 , SOP option to disable BG/MB*/},	\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,		\
	 PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3 \
	 /*0x04[12:11] = 2b'01 enable WL suspend*/},	\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \
	 /*0x04[10] = 1, enable SW LPS*/},	\
        {0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 1 \
	 /*0x48[16] = 1 to enable GPIO9 as EXT WAKEUP*/},   \
	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
	 /*0x23[4] = 1b'1 12H LDO enter sleep mode*/},   \
	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
	PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0 \
	 /*Set SDIO suspend local register*/},	\
	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
	PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0 \
	 /*wait power state to suspend*/},

#define RTL8821A_TRANS_CARDDIS_TO_CARDEMU				\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0 \
	 /*clear suspend enable and power down enable*/},	\
	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
	PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0 \
	 /*Set SDIO suspend local register*/},	\
	{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
	PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1 \
	 /*wait power state to suspend*/},\
	{0x004A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
	 /*0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/},   \
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0 \
	 /*0x04[12:11] = 2b'01enable WL suspend*/},\
	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
	 /*0x23[4] = 1b'0 12H LDO enter normal mode*/},   \
	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
	/*PCIe DMA start*/},

#define RTL8821A_TRANS_CARDEMU_TO_PDN					\
	{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4 \
	 /*0x23[4] = 1b'1 12H LDO enter sleep mode*/},   \
	{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,		\
	 PWR_INTF_SDIO_MSK|PWR_INTF_USB_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x20 \
	 /*0x07[7:0] = 0x20 SOP option to disable BG/MB/ACK/SWR*/},   \
	{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
	/* 0x04[16] = 0*/},\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7 \
	/* 0x04[15] = 1*/},

#define RTL8821A_TRANS_PDN_TO_CARDEMU				\
	{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
	/* 0x04[15] = 0*/},

#define RTL8821A_TRANS_ACT_TO_LPS					\
	{0x0301, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
	/*PCIe DMA stop*/},	\
	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
	/*Tx Pause*/},	\
	{0x05F8, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
	/*Should be zero if no packet is transmitting*/},	\
	{0x05F9, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
	/*Should be zero if no packet is transmitting*/},	\
	{0x05FA, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
	/*Should be zero if no packet is transmitting*/},	\
	{0x05FB, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0 \
	/*Should be zero if no packet is transmitting*/},	\
	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
	/*CCK and OFDM are disabled,and clock are gated*/},	\
	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US \
	/*Delay 1us*/},	\
	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
	/*Whole BB is reset*/},	\
	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x03 \
	/*Reset MAC TRX*/},	\
	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
	/*check if removed later*/},	\
	{0x0093, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x00 \
	/*When driver enter Sus/ Disable, enable LOP for BT*/},	\
	{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5 \
	/*Respond TxOK to scheduler*/},

#define RTL8821A_TRANS_LPS_TO_ACT					\
	{0x0080, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK,\
	PWR_BASEADDR_SDIO, PWR_CMD_WRITE, 0xFF, 0x84 \
	 /*SDIO RPWM*/},\
	{0xFE58, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
	 /*USB RPWM*/},\
	{0x0361, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x84 \
	 /*PCIe RPWM*/},\
	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS \
	 /*Delay*/},\
	{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
	 /*.	0x08[4] = 0		 switch TSF to 40M*/},\
	{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0 \
	 /*Polling 0x109[7]=0  TSF in 40M*/},\
	{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
	 /*.	0x29[7:6] = 2b'00	 enable BB clock*/},\
	{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
	 /*.	0x101[1] = 1*/},\
	{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF \
	 /*.	0x100[7:0] = 0xFF	 enable WMAC TRX*/},\
	{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \
	 /*.	0x02[1:0] = 2b'11	 enable BB macro*/},\
	{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0 \
	 /*.	0x522 = 0*/},

#define RTL8821A_TRANS_END					\
	{0xFFFF, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK,\
	0, PWR_CMD_END, 0, 0},

extern struct wlan_pwr_cfg rtl8821A_power_on_flow
		[RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS +
		 RTL8821A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8821A_radio_off_flow
		[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS +
		 RTL8821A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8821A_card_disable_flow
		[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS +
		 RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS +
		 RTL8821A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8821A_card_enable_flow
		[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS +
		 RTL8821A_TRANS_CARDEMU_TO_ACT_STEPS +
		 RTL8821A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8821A_suspend_flow
		[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS +
		 RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS +
		 RTL8821A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8821A_resume_flow
		[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS +
		 RTL8821A_TRANS_CARDEMU_TO_SUS_STEPS +
		 RTL8821A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8821A_hwpdn_flow
		[RTL8821A_TRANS_ACT_TO_CARDEMU_STEPS +
		 RTL8821A_TRANS_CARDEMU_TO_PDN_STEPS +
		 RTL8821A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8821A_enter_lps_flow
		[RTL8821A_TRANS_ACT_TO_LPS_STEPS +
		 RTL8821A_TRANS_END_STEPS];
extern struct wlan_pwr_cfg rtl8821A_leave_lps_flow
		[RTL8821A_TRANS_LPS_TO_ACT_STEPS +
		 RTL8821A_TRANS_END_STEPS];

/*RTL8812 Power Configuration CMDs for PCIe interface*/
#define RTL8812_NIC_PWR_ON_FLOW			rtl8812_power_on_flow
#define RTL8812_NIC_RF_OFF_FLOW			rtl8812_radio_off_flow
#define RTL8812_NIC_DISABLE_FLOW		rtl8812_card_disable_flow
#define RTL8812_NIC_ENABLE_FLOW			rtl8812_card_enable_flow
#define RTL8812_NIC_SUSPEND_FLOW		rtl8812_suspend_flow
#define RTL8812_NIC_RESUME_FLOW			rtl8812_resume_flow
#define RTL8812_NIC_PDN_FLOW			rtl8812_hwpdn_flow
#define RTL8812_NIC_LPS_ENTER_FLOW		rtl8812_enter_lps_flow
#define RTL8812_NIC_LPS_LEAVE_FLOW		rtl8812_leave_lps_flow

/* RTL8821 Power Configuration CMDs for PCIe interface */
#define RTL8821A_NIC_PWR_ON_FLOW		rtl8821A_power_on_flow
#define RTL8821A_NIC_RF_OFF_FLOW		rtl8821A_radio_off_flow
#define RTL8821A_NIC_DISABLE_FLOW		rtl8821A_card_disable_flow
#define RTL8821A_NIC_ENABLE_FLOW		rtl8821A_card_enable_flow
#define RTL8821A_NIC_SUSPEND_FLOW		rtl8821A_suspend_flow
#define RTL8821A_NIC_RESUME_FLOW		rtl8821A_resume_flow
#define RTL8821A_NIC_PDN_FLOW			rtl8821A_hwpdn_flow
#define RTL8821A_NIC_LPS_ENTER_FLOW		rtl8821A_enter_lps_flow
#define RTL8821A_NIC_LPS_LEAVE_FLOW		rtl8821A_leave_lps_flow

#endif