From 7b3f687b775e4cf7cf9586735504f07695ffa86a Mon Sep 17 00:00:00 2001 From: Piotr Katarzynski Date: Fri, 4 Apr 2014 17:47:19 +0200 Subject: /hal/cortexm/vybrid/../vybrid_misc.c Added new functions for easier GPIO handling --- .../cortexm/vybrid/var/current/include/var_io.h | 4 ++++ .../vybrid/var/current/include/var_io_gpio.h | 7 +++---- .../vybrid/var/current/src/vybrid_clocking.c | 14 ++++++++----- .../cortexm/vybrid/var/current/src/vybrid_misc.c | 23 ++++++++++++++++++++++ 4 files changed, 39 insertions(+), 9 deletions(-) diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io.h b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io.h index 33824f7..aecb238 100644 --- a/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io.h +++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io.h @@ -661,6 +661,10 @@ enum { __externC void hal_set_pin_function(cyg_uint32 pin); __externC void hal_dump_pin_function(cyg_uint32 pin); __externC void hal_dump_pin_setting(cyg_uint32 pin); +__externC void hal_gpio_set_pin(cyg_uint32 pin); +__externC void hal_gpio_clear_pin(cyg_uint32 pin); +__externC void hal_gpio_toggle_pin(cyg_uint32 pin); +__externC cyg_uint32 hal_gpio_get_pin(cyg_uint32 pin); #endif diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io_gpio.h b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io_gpio.h index b5e26bd..694d056 100644 --- a/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io_gpio.h +++ b/ecos/packages/hal/cortexm/vybrid/var/current/include/var_io_gpio.h @@ -86,7 +86,6 @@ PTE27,PTE28,PTA7,NONE #define CYGHWR_HAL_VYBRID_GPIO_PTOR 0x0c #define CYGHWR_HAL_VYBRID_GPIO_PDIR 0x10 - // gets port numer (0,1,2,3) from pin name #define CYGHWR_HAL_VYBRID_GET_PORT(__pin) (vf61_rgpio)__pin >> 5 @@ -103,15 +102,15 @@ PTE27,PTE28,PTA7,NONE #define CYGHWR_HAL_VYBRID_GPIO_GET_PIN(__pin) \ (*((volatile cyg_uint32 *)(CYGHWR_HAL_VYBRID_GET_GPIO(__pin) + CYGHWR_HAL_VYBRID_GPIO_PDIR)) & (1 << CYGHWR_HAL_VYBRID_GET_PIN_LOC(__pin))) -// set pin defined by name +// set pin defined by pad name #define CYGHWR_HAL_VYBRID_GPIO_SET_PIN(__pin) \ HAL_WRITE_UINT32(CYGHWR_HAL_VYBRID_GET_GPIO(__pin) + CYGHWR_HAL_VYBRID_GPIO_PSOR, (1 << (CYGHWR_HAL_VYBRID_GET_PIN_LOC(__pin)))) -// clear pin defined by name +// clear pin defined by pad name #define CYGHWR_HAL_VYBRID_GPIO_CLEAR_PIN(__pin) \ HAL_WRITE_UINT32(CYGHWR_HAL_VYBRID_GET_GPIO(__pin) + CYGHWR_HAL_VYBRID_GPIO_PCOR, (1 << (CYGHWR_HAL_VYBRID_GET_PIN_LOC(__pin)))) -// toggle pin defined by name +// toggle pin defined by pad name #define CYGHWR_HAL_VYBRID_GPIO_TOGGLE_PIN(__pin) \ HAL_WRITE_UINT32(CYGHWR_HAL_VYBRID_GET_GPIO(__pin) + CYGHWR_HAL_VYBRID_GPIO_PTOR, (1 << (CYGHWR_HAL_VYBRID_GET_PIN_LOC(__pin)))) diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_clocking.c b/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_clocking.c index 3aac8ed..d001f27 100644 --- a/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_clocking.c +++ b/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_clocking.c @@ -114,8 +114,8 @@ hal_get_cpu_clock(void) //PFDout = PLLput * (18 / PFD_FRAC) freq /= pfd; freq *= 18; + break; } - break; // Fall down as the pfd_sel == 0 selects PLL2 main clock case 3: // PLL2 main clock // check if PLL2 is bypassed @@ -133,7 +133,7 @@ hal_get_cpu_clock(void) mfi &= CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_DIV_SELECT_M; // if CYGHWR_HAL_VYBRID_ANADIG_PLL2_CTRL_DIV_SELECT is set, then mfi is 22 mfi = (mfi ? 22 : 20); - // calculate the PLL! frequency + // calculate the PLL2 frequency freq = (24000000 * (mfi + (mfn / mfd))); break; case 4: // PLL1 PFD o/p clock defined by CCM_CCSR[PLL1_PFD_CLK_SEL] @@ -155,7 +155,6 @@ hal_get_cpu_clock(void) freq /= pfd; freq *= 18; } - //TODO: handle the PLL1 main clk break; case 5: // PLL3 main clock HAL_READ_UINT32(CYGHWR_HAL_VYBRID_ANADIG_PLL3_CTRL, mfi); @@ -219,9 +218,14 @@ hal_freescale_uart_setbaud(cyg_uint32 uart_p, cyg_uint32 baud) void hal_update_clock_var(void) { + cyghwr_hal_vybrid_ccm_t *ccm = CYGHWR_HAL_VYBRID_CCM_P; + cyg_uint32 ipg_clk_div; + + ipg_clk_div = (ccm->cacrr & CYGHWR_HAL_VYBRID_CCM_CACRR_IPG_CLK_DIV_M); + ipg_clk_div = (ipg_clk_div >> CYGHWR_HAL_VYBRID_CCM_CACRR_IPG_CLK_DIV_S); + hal_vybrid_sysclk = hal_get_cpu_clock(); - hal_vybrid_busclk = hal_vybrid_sysclk / - 2; //TODO: place option for selecting CCM_CACRR[IPG_CLK_DIV] from CDL + hal_vybrid_busclk = hal_vybrid_sysclk / (ipg_clk_div + 1); hal_cortexm_systick_clock = hal_vybrid_sysclk; } diff --git a/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_misc.c b/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_misc.c index aa0e4fa..2d0f666 100644 --- a/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_misc.c +++ b/ecos/packages/hal/cortexm/vybrid/var/current/src/vybrid_misc.c @@ -196,6 +196,29 @@ hal_dump_pin_function(cyg_uint32 pin) diag_printf("Pin PT%c%d: IOMUX=0x08%x\n",0x41+port,bit,mux_val); } +inline void +hal_gpio_set_pin(cyg_uint32 pin) +{ + CYGHWR_HAL_VYBRID_GPIO_SET_PIN(vf61_pads[CYGHWR_HAL_VYBRID_PIN_PORT(pin)*32+CYGHWR_HAL_VYBRID_PIN_BIT(pin)]); +} + +inline void +hal_gpio_clear_pin(cyg_uint32 pin) +{ + CYGHWR_HAL_VYBRID_GPIO_CLEAR_PIN(vf61_pads[CYGHWR_HAL_VYBRID_PIN_PORT(pin)*32+CYGHWR_HAL_VYBRID_PIN_BIT(pin)]); +} + +inline void +hal_gpio_toggle_pin(cyg_uint32 pin) +{ + CYGHWR_HAL_VYBRID_GPIO_TOGGLE_PIN(vf61_pads[CYGHWR_HAL_VYBRID_PIN_PORT(pin)*32+CYGHWR_HAL_VYBRID_PIN_BIT(pin)]); +} + +inline cyg_uint32 +hal_gpio_get_pin(cyg_uint32 pin) +{ + return CYGHWR_HAL_VYBRID_GPIO_GET_PIN(vf61_pads[CYGHWR_HAL_VYBRID_PIN_PORT(pin)*32+CYGHWR_HAL_VYBRID_PIN_BIT(pin)])?1:0; +} //========================================================================== // VYBRID Clock distribution //========================================================================== -- cgit v1.2.3