#ifndef CYGONCE_HAL_VAR_IOCLKGAT_H
#define CYGONCE_HAL_VAR_IOCLKGAT_H
//===========================================================================
//
//      var_io_clkgat.h
//
//      Vybrid clock gating
//
//===========================================================================
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// -------------------------------------------                              
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// Copyright (C) 2013 Free Software Foundation, Inc.                        
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//
// As a special exception, if other files instantiate templates or use      
// macros or inline functions from this file, or you compile this file      
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// this file does not by itself cause the resulting work to be covered by   
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//===========================================================================
//#####DESCRIPTIONBEGIN####
//
// Author(s):    Antmicro Ltd <contact@antmicro.com>
// Based on:	 {...}/hal/packages/cortexm/kinetis/var/current/include/var_io_clkgat.h
// Date:         2014-03-28
// Purpose:      Vybrid clock distribution macros
// Description:
// Usage:         This file is included by <cyg/hal/var_io.h>
//
//####DESCRIPTIONEND####
//
//===========================================================================

//---------------------------------------------------------------------------
// Clock distribution

// Clock gating definitions
#define CYGHWR_HAL_VYBRID_CCM_CCGR_UART0 CYGHWR_HAL_VYBRID_CCM_CCGR(0, 7)
#define CYGHWR_HAL_VYBRID_CCM_CCGR_UART1 CYGHWR_HAL_VYBRID_CCM_CCGR(0, 8)
#define CYGHWR_HAL_VYBRID_CCM_CCGR_UART2 CYGHWR_HAL_VYBRID_CCM_CCGR(0, 9)
#define CYGHWR_HAL_VYBRID_CCM_CCGR_UART3 CYGHWR_HAL_VYBRID_CCM_CCGR(0, 10)
#define CYGHWR_HAL_VYBRID_CCM_CCGR_UART4 CYGHWR_HAL_VYBRID_CCM_CCGR(6, 105)
#define CYGHWR_HAL_VYBRID_CCM_CCGR_UART5 CYGHWR_HAL_VYBRID_CCM_CCGR(6, 106)


#endif // CYGONCE_HAL_VAR_IOCLKGAT_H