diff options
| author | Stefan Agner <stefan.agner@toradex.com> | 2018-05-29 11:28:18 +0200 |
|---|---|---|
| committer | Stefan Agner <stefan.agner@toradex.com> | 2018-05-29 11:28:18 +0200 |
| commit | 1a503cf169b7c46e2f749d85fd0310b8e38fb355 (patch) | |
| tree | 3104527c24b168e12aaaeedea65ac78c7286502b | |
| parent | 33f9cdf13af7828952c47a702c5f5244091473f9 (diff) | |
fix FlexCAN1 pinmuxing
Make sure the correct alternate mode is choosen and RX pin daisy
chaining is taken care of.
Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
| -rw-r--r-- | examples/imx7_colibri_m4/pin_mux.c | 19 |
1 files changed, 11 insertions, 8 deletions
diff --git a/examples/imx7_colibri_m4/pin_mux.c b/examples/imx7_colibri_m4/pin_mux.c index 8dc611d..1bb007e 100644 --- a/examples/imx7_colibri_m4/pin_mux.c +++ b/examples/imx7_colibri_m4/pin_mux.c @@ -43,19 +43,21 @@ void configure_flexcan_pins(CAN_Type* base) switch((uint32_t)base) { case CAN1_BASE: - // CAN1_TX SODIMM 63 - IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2 = IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2_MUX_MODE(3); + // CAN1_TX SODIMM 55 + IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3 = IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3_MUX_MODE(1); + IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3 = IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_PE_MASK | + IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_PS(3) | + IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_DSE(0) | + IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_HYS_MASK; + + // CAN1_RX SODIMM 63 + IOMUXC_FLEXCAN1_RX_SELECT_INPUT = 0x4; + IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2 = IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2_MUX_MODE(1); IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2 = IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_PE_MASK | IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_PS(3) | IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_DSE(0) | IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_HYS_MASK; - // CAN1_RX SODIMM 55 - IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3 = IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3_MUX_MODE(3); - IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3 = IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_PE_MASK | - IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_PS(3) | - IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_DSE(0) | - IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_HYS_MASK; break; case CAN2_BASE: // CAN2_TX SODIMM 178 @@ -66,6 +68,7 @@ void configure_flexcan_pins(CAN_Type* base) IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_HYS_MASK; // CAN2_RX SODIMM 188 + IOMUXC_FLEXCAN2_RX_SELECT_INPUT = 0x0; IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14 = IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_MUX_MODE(3); IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14 = IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_PE_MASK | IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_PS(3) | |