From 3020f5caf0b09fcaf85b3b3fa84fdf688ba22cc0 Mon Sep 17 00:00:00 2001 From: Dominik Sliwa Date: Thu, 9 Nov 2017 19:51:32 +0100 Subject: K20: can and spi fixes Signed-off-by: Dominik Sliwa --- source/com_task.c | 88 +++++++++++++++++++++++++++++++++++-------------------- 1 file changed, 56 insertions(+), 32 deletions(-) (limited to 'source/com_task.c') diff --git a/source/com_task.c b/source/com_task.c index 01796d8..9edc906 100644 --- a/source/com_task.c +++ b/source/com_task.c @@ -5,7 +5,7 @@ #include "adc_task.h" /* Put FW version at known address in binary. Make it 32-bit to have room for the future*/ -const uint32_t __attribute__((section(".FwVersion"))) fw_version = APALIS_TK1_K20_FW_VER; +const uint32_t __attribute__((section(".FwVersion"), used)) fw_version = APALIS_TK1_K20_FW_VER; static dspi_slave_handle_t spi_handle; static uint8_t slaveRxData[APALIS_TK1_K20_MAX_BULK + APALIS_TK1_K20_HEADER] = {0U}; @@ -67,13 +67,13 @@ void set_irq_reg(uint8_t value) } -inline int general_registers(dspi_transfer_t *spi_transfer) +inline int general_registers(dspi_transfer_t * spi_transfer) { uint8_t *rx_buf = spi_transfer->rxData; uint8_t *tx_buf = &spi_transfer->txData[1]; if (rx_buf[0] == APALIS_TK1_K20_READ_INST) { - switch (rx_buf[1]) { + switch (rx_buf[2]) { case APALIS_TK1_K20_STAREG: tx_buf[0] = get_status_reg(); return 1; @@ -96,18 +96,18 @@ inline int general_registers(dspi_transfer_t *spi_transfer) switch (rx_buf[1]) { case APALIS_TK1_K20_STAREG: set_status_reg(rx_buf[2]); - return 0; + return 1; case APALIS_TK1_K20_REVREG: return -ENOENT; case APALIS_TK1_K20_IRQREG: set_irq_reg(rx_buf[2]); - return 0; + return 1; case APALIS_TK1_K20_CTRREG: set_control_reg(rx_buf[2]); - return 0; + return 1; case APALIS_TK1_K20_MSQREG: set_mask_reg(rx_buf[2]); - return 0; + return 1; default: return -ENOENT; } @@ -134,19 +134,24 @@ static void SPI_callback(SPI_Type *base, dspi_slave_handle_t *handle, status_t s portYIELD_FROM_ISR(reschedule); } +static dspi_slave_config_t spi2_slaveConfig; + static void SPI_init() { - dspi_slave_config_t slaveConfig; + gpio_pin_config_t gpio_out_config = { + kGPIO_DigitalOutput, 0, + }; + GPIO_PinInit(GPIOD, 11u, &gpio_out_config); /* Slave config */ - slaveConfig.whichCtar = kDSPI_Ctar0; - slaveConfig.ctarConfig.bitsPerFrame = 8; - slaveConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; - slaveConfig.ctarConfig.cpha = kDSPI_ClockPhaseSecondEdge; - slaveConfig.enableContinuousSCK = true; - slaveConfig.enableRxFifoOverWrite = false; - slaveConfig.enableModifiedTimingFormat = false; - slaveConfig.samplePoint = kDSPI_SckToSin0Clock; - - DSPI_SlaveInit(SPI2, &slaveConfig); + spi2_slaveConfig.whichCtar = kDSPI_Ctar0; + spi2_slaveConfig.ctarConfig.bitsPerFrame = 8; + spi2_slaveConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; + spi2_slaveConfig.ctarConfig.cpha = kDSPI_ClockPhaseSecondEdge; + spi2_slaveConfig.enableContinuousSCK = false; + spi2_slaveConfig.enableRxFifoOverWrite = true; + spi2_slaveConfig.enableModifiedTimingFormat = false; + spi2_slaveConfig.samplePoint = kDSPI_SckToSin0Clock; + PRINTF("SPI init \r\n"); + DSPI_SlaveInit(SPI2, &spi2_slaveConfig); DSPI_SlaveTransferCreateHandle(SPI2, &spi_handle, SPI_callback, spi_handle.userData); /* Set dspi slave interrupt priority higher. */ @@ -159,7 +164,8 @@ static void SPI_init() { void spi_task(void *pvParameters) { callback_message_t cb_msg; dspi_transfer_t slaveXfer; - int ret; + int ret, retry_size = 0; + uint8_t req_register = 0xFF; cb_msg.sem = xSemaphoreCreateBinary(); spi_handle.userData = &cb_msg; @@ -167,38 +173,53 @@ void spi_task(void *pvParameters) { GPIO_SetPinsOutput(GPIOA, 1u << 29u); /* INT2 idle */ while(1){ - slaveXfer.txData = slaveTxData; + slaveXfer.txData = NULL;/* We're not expecting any MISO traffic */ slaveXfer.rxData = slaveRxData; slaveXfer.dataSize = 3; slaveXfer.configFlags = kDSPI_SlaveCtar0; /* Wait for instructions from SoC */ DSPI_SlaveTransferNonBlocking(SPI2, &spi_handle, &slaveXfer); xSemaphoreTake(cb_msg.sem, portMAX_DELAY); - if (slaveRxData[1] <= 0x05) { + GPIO_ClearPinsOutput(GPIOD, 1u << 11u); + slaveXfer.txData = slaveTxData; + slaveXfer.rxData = slaveRxData; + + if (slaveRxData[0] == APALIS_TK1_K20_WRITE_INST) + req_register = slaveRxData[1]; + else + req_register = slaveRxData[2]; + + if (req_register <= 0x05) { ret = general_registers(&slaveXfer); - } else if ((slaveRxData[1] >= APALIS_TK1_K20_CANREG + APALIS_TK1_K20_CAN_DEV_OFFSET(0)) - && (slaveRxData[1] <= APALIS_TK1_K20_CAN_OUT_BUF_END + APALIS_TK1_K20_CAN_DEV_OFFSET(0))) { - ret = can0_registers(&slaveXfer); + } else if ((req_register >= APALIS_TK1_K20_CANREG + APALIS_TK1_K20_CAN_DEV_OFFSET(0)) + && (req_register <= APALIS_TK1_K20_CAN_OUT_BUF_END + APALIS_TK1_K20_CAN_DEV_OFFSET(0))) { + ret = canx_registers(&slaveXfer, 0); - } else if ((slaveRxData[1] >= APALIS_TK1_K20_CANREG + APALIS_TK1_K20_CAN_DEV_OFFSET(1)) - && (slaveRxData[1] <= APALIS_TK1_K20_CAN_OUT_BUF_END + APALIS_TK1_K20_CAN_DEV_OFFSET(1))) { - ret = can1_registers(&slaveXfer); + } else if ((req_register >= APALIS_TK1_K20_CANREG + APALIS_TK1_K20_CAN_DEV_OFFSET(1)) + && (req_register <= APALIS_TK1_K20_CAN_OUT_BUF_END + APALIS_TK1_K20_CAN_DEV_OFFSET(1))) { + ret = canx_registers(&slaveXfer, 1); #ifdef BOARD_USES_ADC - } else if ((slaveRxData[1] >= APALIS_TK1_K20_ADCREG) && (slaveRxData[1] <= APALIS_TK1_K20_ADC_CH3H)) { + } else if ((req_register >= APALIS_TK1_K20_ADCREG) && (req_register <= APALIS_TK1_K20_ADC_CH3H)) { ret = adc_registers(&slaveXfer); - } else if ((slaveRxData[1] >= APALIS_TK1_K20_TSCREG) && (slaveRxData[1] <= APALIS_TK1_K20_TSC_YPH)) { + } else if ((req_register >= APALIS_TK1_K20_TSCREG) && (req_register <= APALIS_TK1_K20_TSC_YPH)) { ret = tsc_registers(&slaveXfer); #endif - } else if ((slaveRxData[1] >= APALIS_TK1_K20_GPIOREG) && (slaveRxData[1] <= APALIS_TK1_K20_GPIO_STA)) { + } else if ((req_register >= APALIS_TK1_K20_GPIOREG) && (req_register <= APALIS_TK1_K20_GPIO_STA)) { ret = gpio_registers(&slaveXfer); + } else if (req_register == APALIS_TK1_K20_RET_REQ) { + /* something wrong with the SPI peripheral, try resetting it */ + DSPI_StopTransfer(SPI2); + DSPI_Enable(SPI2, false); + DSPI_SlaveInit(SPI2, &spi2_slaveConfig); + ret = retry_size - 1; } else { /* Register not defined */ ret = -EINVAL; } - if (ret < 0) { + if (ret <= 0) { slaveTxData[0] = TK1_K20_INVAL; slaveTxData[1] = TK1_K20_INVAL; } else { @@ -207,8 +228,11 @@ void spi_task(void *pvParameters) { if (slaveRxData[0] == APALIS_TK1_K20_READ_INST || slaveRxData[0] == APALIS_TK1_K20_BULK_READ_INST) { - slaveXfer.dataSize = (ret >= 0) ? (ret + 1):2; /* Extra byte is for sentinel */ + slaveXfer.dataSize = (ret > 0) ? (ret + 1):2; /* Extra byte is for sentinel*/ + retry_size = slaveXfer.dataSize; + slaveXfer.rxData = NULL; /* We're not expecting any MOSI traffic */ DSPI_SlaveTransferNonBlocking(SPI2, &spi_handle, &slaveXfer); + GPIO_SetPinsOutput(GPIOD, 1u << 11u); xSemaphoreTake(cb_msg.sem, portMAX_DELAY); } } -- cgit v1.2.3