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| author | davidcunado-arm <david.cunado@arm.com> | 2018-02-26 10:42:55 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-02-26 10:42:55 +0000 |
| commit | 5ff6da948710361dec294f4b5106978501531caf (patch) | |
| tree | eb8423c1ec4682b4adabe01a4d96474a652aa974 | |
| parent | 4b26f79ac0b36a7a16d8b58057f8142a68f318ac (diff) | |
| parent | 6bf0e079303545ad6dd314ce3e7cb3a11dcec413 (diff) | |
Merge pull request #1273 from antonio-nino-diaz-arm/an/fix-tlbi-disable-mmu
Ensure the correct execution of TLBI instructions
| -rw-r--r-- | bl1/aarch64/bl1_exceptions.S | 1 | ||||
| -rw-r--r-- | plat/rockchip/rk3328/drivers/pmu/pmu.c | 4 | ||||
| -rw-r--r-- | services/std_svc/spm/secure_partition_setup.c | 1 |
3 files changed, 5 insertions, 1 deletions
diff --git a/bl1/aarch64/bl1_exceptions.S b/bl1/aarch64/bl1_exceptions.S index eb98ffa0..92313fa3 100644 --- a/bl1/aarch64/bl1_exceptions.S +++ b/bl1/aarch64/bl1_exceptions.S @@ -187,6 +187,7 @@ func smc_handler64 bl disable_mmu_icache_el3 tlbi alle3 + dsb ish /* ERET implies ISB, so it is not needed here */ #if SPIN_ON_BL1_EXIT bl print_debug_loop_message diff --git a/plat/rockchip/rk3328/drivers/pmu/pmu.c b/plat/rockchip/rk3328/drivers/pmu/pmu.c index f576fe41..835c3a6b 100644 --- a/plat/rockchip/rk3328/drivers/pmu/pmu.c +++ b/plat/rockchip/rk3328/drivers/pmu/pmu.c @@ -591,8 +591,10 @@ err_loop: __sramfunc void sram_suspend(void) { /* disable mmu and icache */ - tlbialle3(); disable_mmu_icache_el3(); + tlbialle3(); + dsbsy(); + isb(); mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1), ((uintptr_t)&pmu_cpuson_entrypoint >> CPU_BOOT_ADDR_ALIGN) | diff --git a/services/std_svc/spm/secure_partition_setup.c b/services/std_svc/spm/secure_partition_setup.c index c1f0edf6..6998dae5 100644 --- a/services/std_svc/spm/secure_partition_setup.c +++ b/services/std_svc/spm/secure_partition_setup.c @@ -54,6 +54,7 @@ void secure_partition_setup(void) /* Invalidate TLBs at EL1. */ tlbivmalle1(); + dsbish(); /* * General-Purpose registers |