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author | Bai Ping <ping.bai@nxp.com> | 2017-08-28 14:22:15 +0800 |
---|---|---|
committer | Bai Ping <ping.bai@nxp.com> | 2017-08-28 14:25:54 +0800 |
commit | 96f4d3768c8b35d2d8cbcce75617790f3bb037f6 (patch) | |
tree | 9fe5784ab03c179338ee6e9f31fb950fdb57877a | |
parent | 61d8cbdf027c0b00ca4c2dbe00d6e0b896cc7b42 (diff) |
fix sw pup/pdn issue on imx8mq
The bits[3:0] of CPU_PGC_PUP/PDN_TRG use core's SW
power up/down. prevous bits assignment is wrong, so
fix it.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
-rw-r--r-- | plat/freescale/imx8mq/gpc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/plat/freescale/imx8mq/gpc.c b/plat/freescale/imx8mq/gpc.c index b3ddd770..c1836d93 100644 --- a/plat/freescale/imx8mq/gpc.c +++ b/plat/freescale/imx8mq/gpc.c @@ -270,7 +270,7 @@ void imx_gpc_set_core_pdn_pup_by_software(unsigned int cpu, bool pdn) /*Set the core PCR bit before sw PUP/PDN trigger */ imx_gpc_set_m_core_pgc(GPC_ARM_PGC + cpu * 0x40, true); - index = cpu < 2 ? cpu : cpu + 1; + index = cpu; val |= (BM_CPU_PGC_SW_PDN_PUP_REQ << index); mmio_write_32(IMX_GPC_BASE + (pdn ? GPC_CPU_PGC_SW_PDN_REQ : GPC_CPU_PGC_SW_PUP_REQ), val); |