diff options
| author | Antonio Nino Diaz <antonio.ninodiaz@arm.com> | 2018-02-19 13:53:48 +0000 |
|---|---|---|
| committer | Antonio Nino Diaz <antonio.ninodiaz@arm.com> | 2018-02-21 13:54:55 +0000 |
| commit | 6bf0e079303545ad6dd314ce3e7cb3a11dcec413 (patch) | |
| tree | 25ea1d115147da95470962d9098063ed770a750d /bl1 | |
| parent | 5ff5a6d9c33fdf8b626a4e61066f467f2b5c75a9 (diff) | |
Ensure the correct execution of TLBI instructions
After executing a TLBI a DSB is needed to ensure completion of the
TLBI.
rk3328: The MMU is allowed to load TLB entries for as long as it is
enabled. Because of this, the correct place to execute a TLBI is right
after disabling the MMU.
Change-Id: I8280f248d10b49a8c354a4ccbdc8f8345ac4c170
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Diffstat (limited to 'bl1')
| -rw-r--r-- | bl1/aarch64/bl1_exceptions.S | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/bl1/aarch64/bl1_exceptions.S b/bl1/aarch64/bl1_exceptions.S index eb98ffa0..92313fa3 100644 --- a/bl1/aarch64/bl1_exceptions.S +++ b/bl1/aarch64/bl1_exceptions.S @@ -187,6 +187,7 @@ func smc_handler64 bl disable_mmu_icache_el3 tlbi alle3 + dsb ish /* ERET implies ISB, so it is not needed here */ #if SPIN_ON_BL1_EXIT bl print_debug_loop_message |