diff options
| author | Achin Gupta <achin.gupta@arm.com> | 2014-08-04 23:13:10 +0100 |
|---|---|---|
| committer | Achin Gupta <achin.gupta@arm.com> | 2014-08-15 10:21:50 +0100 |
| commit | 0c8d4fef28768233f1f46b4d085f904293dffd2c (patch) | |
| tree | f921b7d842ce3a7be0e7e701f35fbea187e8dee6 /bl32/tsp | |
| parent | c1efc4c0666b95912b54e079de484d8c2249e045 (diff) | |
Unmask SError interrupt and clear SCR_EL3.EA bit
This patch disables routing of external aborts from lower exception levels to
EL3 and ensures that a SError interrupt generated as a result of execution in
EL3 is taken locally instead of a lower exception level.
The SError interrupt is enabled in the TSP code only when the operation has not
been directly initiated by the normal world. This is to prevent the possibility
of an asynchronous external abort which originated in normal world from being
taken when execution is in S-EL1.
Fixes ARM-software/tf-issues#153
Change-Id: I157b996c75996d12fd86d27e98bc73dd8bce6cd5
Diffstat (limited to 'bl32/tsp')
| -rw-r--r-- | bl32/tsp/aarch64/tsp_entrypoint.S | 12 | ||||
| -rw-r--r-- | bl32/tsp/aarch64/tsp_exceptions.S | 6 |
2 files changed, 18 insertions, 0 deletions
diff --git a/bl32/tsp/aarch64/tsp_entrypoint.S b/bl32/tsp/aarch64/tsp_entrypoint.S index 75ee4434..002c41b8 100644 --- a/bl32/tsp/aarch64/tsp_entrypoint.S +++ b/bl32/tsp/aarch64/tsp_entrypoint.S @@ -77,6 +77,14 @@ func tsp_entrypoint */ adr x0, tsp_exceptions msr vbar_el1, x0 + isb + + /* --------------------------------------------- + * Enable the SError interrupt now that the + * exception vectors have been setup. + * --------------------------------------------- + */ + msr daifclr, #DAIF_ABT_BIT /* --------------------------------------------- * Enable the instruction cache, stack pointer @@ -186,6 +194,10 @@ func tsp_cpu_on_entry */ adr x0, tsp_exceptions msr vbar_el1, x0 + isb + + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT /* --------------------------------------------- * Enable the instruction cache, stack pointer diff --git a/bl32/tsp/aarch64/tsp_exceptions.S b/bl32/tsp/aarch64/tsp_exceptions.S index f84b5e09..4c0d4361 100644 --- a/bl32/tsp/aarch64/tsp_exceptions.S +++ b/bl32/tsp/aarch64/tsp_exceptions.S @@ -120,6 +120,9 @@ sync_exception_sp_elx: .align 7 irq_sp_elx: + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT + save_caller_regs_and_lr /* We just update some statistics in the handler */ bl tsp_irq_received @@ -132,6 +135,9 @@ irq_sp_elx: .align 7 fiq_sp_elx: + /* Enable the SError interrupt */ + msr daifclr, #DAIF_ABT_BIT + save_caller_regs_and_lr bl tsp_fiq_handler cbz x0, fiq_sp_elx_done |