diff options
| author | Yatharth Kochar <yatharth.kochar@arm.com> | 2016-11-09 15:39:25 +0000 |
|---|---|---|
| committer | Yatharth Kochar <yatharth.kochar@arm.com> | 2016-12-01 11:02:51 +0000 |
| commit | 69d59e0ce9f713b0fd4929908ec1649d29f2cbd4 (patch) | |
| tree | fde05328ab9626b1aecdeff086b49c4fb81cc277 /drivers/arm | |
| parent | c59428b1502f37c9b2f551613da1b491c4226d10 (diff) | |
AArch32: Miscellaneous fixes in the AArch32 code
This patch makes following miscellaneous fixes:
* pl011_console.S: Fixed the bit mask used to check if the
transmit FIFO is full or empty.
* smcc_macros.S: Added `_fsxc` suffix while updating the SPSR.
By default the assembler assumes `_fc` suffix which does not
update all the fields in SPSR. By adding `_fsxc` suffix all
the fields gets updated.
* platform_helpers.S: Removed the weak definition for
`plat_my_core_pos()` as this is a mandatory function which
needs to be defined by all platforms.
Change-Id: I8302292533c943686fff8d7c749a07132c052a3b
Signed-off-by: Yatharth Kochar <yatharth.kochar@arm.com>
Diffstat (limited to 'drivers/arm')
| -rw-r--r-- | drivers/arm/pl011/aarch32/pl011_console.S | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/arm/pl011/aarch32/pl011_console.S b/drivers/arm/pl011/aarch32/pl011_console.S index 21ed7ab8..5b735283 100644 --- a/drivers/arm/pl011/aarch32/pl011_console.S +++ b/drivers/arm/pl011/aarch32/pl011_console.S @@ -118,15 +118,15 @@ func console_core_putc 1: /* Check if the transmit FIFO is full */ ldr r2, [r1, #UARTFR] - tst r2, #PL011_UARTFR_TXFF_BIT - beq 1b + tst r2, #PL011_UARTFR_TXFF + bne 1b mov r2, #0xD str r2, [r1, #UARTDR] 2: /* Check if the transmit FIFO is full */ ldr r2, [r1, #UARTFR] - tst r2, #PL011_UARTFR_TXFF_BIT - beq 2b + tst r2, #PL011_UARTFR_TXFF + bne 2b str r0, [r1, #UARTDR] bx lr putc_error: @@ -149,8 +149,8 @@ func console_core_getc 1: /* Check if the receive FIFO is empty */ ldr r1, [r0, #UARTFR] - tst r1, #PL011_UARTFR_RXFE_BIT - beq 1b + tst r1, #PL011_UARTFR_RXFE + bne 1b ldr r1, [r0, #UARTDR] mov r0, r1 bx lr |