diff options
author | Nishanth Menon <nm@ti.com> | 2017-01-10 09:34:07 -0600 |
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committer | Nishanth Menon <nm@ti.com> | 2017-01-10 09:36:44 -0600 |
commit | 861ac52a7e80c0399b6e543e7125a9c1e18a63f8 (patch) | |
tree | 4d735faceb0449e4de072adc56e60e88d105a69f /drivers/ti | |
parent | 176129530e80491a789ea6402a18b65834c7fe54 (diff) |
uart: 16550: Fix getc
tbz check for RDR status is to check for a bit being zero.
Unfortunately, we are using a mask rather than the bit position.
Further as per http://www.ti.com/lit/ds/symlink/pc16550d.pdf (page 17),
LSR register bit 0 is Data ready status (RDR), not bit position 2.
Update the same to match the specification.
Reported-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'drivers/ti')
-rw-r--r-- | drivers/ti/uart/aarch64/16550_console.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/ti/uart/aarch64/16550_console.S b/drivers/ti/uart/aarch64/16550_console.S index 05353814..84664829 100644 --- a/drivers/ti/uart/aarch64/16550_console.S +++ b/drivers/ti/uart/aarch64/16550_console.S @@ -146,7 +146,7 @@ endfunc console_core_putc func console_core_getc /* Check if the receive FIFO is empty */ 1: ldr w1, [x0, #UARTLSR] - tbz w1, #UARTLSR_RDR, 1b + tbz w1, #UARTLSR_RDR_BIT, 1b ldr w0, [x0, #UARTRX] ret getc_error: |