diff options
| author | Manoj Kumar <manoj.kumar3@arm.com> | 2018-01-19 17:51:31 +0530 |
|---|---|---|
| committer | Manoj Kumar <manoj.kumar3@arm.com> | 2018-01-19 17:51:31 +0530 |
| commit | 2dc80e493124369f44658fcce325dc2cda00b410 (patch) | |
| tree | 7773415d44a0a348f68a5612386a9d4d54bf5aee /lib | |
| parent | 9fd4a36c408a254d887106e6e3960d496456be2c (diff) | |
lib/cpus: fix branching in reset function for cortex-a72 AARCH32 mode
In AARCH32 mode, cortex_a72_reset_func branches to address in lr
register instead of r5 register. This leads to linux boot failure
of Cortex-A72 cores in AARCH32 mode on Juno-R2 board.
This patch fixes the branching of cortex_a72_reset_func to r5
register as in cortex_a57_reset_func implementation.
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/cpus/aarch32/cortex_a72.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/cpus/aarch32/cortex_a72.S b/lib/cpus/aarch32/cortex_a72.S index 75505206..35b9bc2e 100644 --- a/lib/cpus/aarch32/cortex_a72.S +++ b/lib/cpus/aarch32/cortex_a72.S @@ -109,7 +109,7 @@ func cortex_a72_reset_func orr64_imm r0, r1, CORTEX_A72_ECTLR_SMP_BIT stcopr16 r0, r1, CORTEX_A72_ECTLR isb - bx lr + bx r5 endfunc cortex_a72_reset_func /* ---------------------------------------------------- |