diff options
| author | davidcunado-arm <david.cunado@arm.com> | 2018-02-28 01:26:21 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-02-28 01:26:21 +0000 |
| commit | c69145fc2a8f1660131f555f286c6989c8343c74 (patch) | |
| tree | 57f5e8ea7244c33953999e97299b482fbe67a433 /lib | |
| parent | 99e198ecd869d33a5948445dd17c5e0920ef5477 (diff) | |
| parent | 264410306381d4edceeb03b3a0e8db66605427be (diff) | |
Merge pull request #1286 from antonio-nino-diaz-arm/an/mmu-mismatch
Clarify comments in xlat tables lib and fixes related to the TLB
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/psci/aarch32/psci_helpers.S | 24 | ||||
| -rw-r--r-- | lib/psci/aarch64/psci_helpers.S | 24 |
2 files changed, 46 insertions, 2 deletions
diff --git a/lib/psci/aarch32/psci_helpers.S b/lib/psci/aarch32/psci_helpers.S index 9373d4f1..a29a29c4 100644 --- a/lib/psci/aarch32/psci_helpers.S +++ b/lib/psci/aarch32/psci_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -91,6 +91,28 @@ func psci_do_pwrup_cache_maintenance stcopr r0, SCTLR isb +#if PLAT_XLAT_TABLES_DYNAMIC + /* --------------------------------------------- + * During warm boot the MMU is enabled with data + * cache disabled, then the interconnect is set + * up and finally the data cache is enabled. + * + * During this period, if another CPU modifies + * the translation tables, the MMU table walker + * may read the old entries. This is only a + * problem for dynamic regions, the warm boot + * code isn't affected because it is static. + * + * Invalidate all TLB entries loaded while the + * CPU wasn't coherent with the rest of the + * system. + * --------------------------------------------- + */ + stcopr r0, TLBIALL + dsb ish + isb +#endif + pop {r12, pc} endfunc psci_do_pwrup_cache_maintenance diff --git a/lib/psci/aarch64/psci_helpers.S b/lib/psci/aarch64/psci_helpers.S index afe21ebe..d37ca764 100644 --- a/lib/psci/aarch64/psci_helpers.S +++ b/lib/psci/aarch64/psci_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -115,6 +115,28 @@ func psci_do_pwrup_cache_maintenance msr sctlr_el3, x0 isb +#if PLAT_XLAT_TABLES_DYNAMIC + /* --------------------------------------------- + * During warm boot the MMU is enabled with data + * cache disabled, then the interconnect is set + * up and finally the data cache is enabled. + * + * During this period, if another CPU modifies + * the translation tables, the MMU table walker + * may read the old entries. This is only a + * problem for dynamic regions, the warm boot + * code isn't affected because it is static. + * + * Invalidate all TLB entries loaded while the + * CPU wasn't coherent with the rest of the + * system. + * --------------------------------------------- + */ + tlbi alle3 + dsb ish + isb +#endif + ldp x29, x30, [sp], #16 ret endfunc psci_do_pwrup_cache_maintenance |