diff options
author | Dimitris Papastamos <dimitris.papastamos@arm.com> | 2017-10-17 14:03:14 +0100 |
---|---|---|
committer | Dimitris Papastamos <dimitris.papastamos@arm.com> | 2017-11-29 09:36:35 +0000 |
commit | ef69e1ea629542865f2c9b04df578aaa3966fb6a (patch) | |
tree | 18ffa579368d4c21243b86f2a4bd6e051f1637e6 /lib | |
parent | 380559c1c3ac80c0d2581a931c80323d1fefbfd6 (diff) |
AMU: Implement support for aarch32
The `ENABLE_AMU` build option can be used to enable the
architecturally defined AMU counters. At present, there is no support
for the auxiliary counter group.
Change-Id: Ifc7532ef836f83e629f2a146739ab61e75c4abc8
Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
Diffstat (limited to 'lib')
-rw-r--r-- | lib/el3_runtime/aarch32/context_mgmt.c | 4 | ||||
-rw-r--r-- | lib/extensions/amu/aarch32/amu.c | 32 |
2 files changed, 36 insertions, 0 deletions
diff --git a/lib/el3_runtime/aarch32/context_mgmt.c b/lib/el3_runtime/aarch32/context_mgmt.c index a8672d6c..76e440e3 100644 --- a/lib/el3_runtime/aarch32/context_mgmt.c +++ b/lib/el3_runtime/aarch32/context_mgmt.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause */ +#include <amu.h> #include <arch.h> #include <arch_helpers.h> #include <assert.h> @@ -132,6 +133,9 @@ static void cm_init_context_common(cpu_context_t *ctx, const entry_point_info_t static void enable_extensions_nonsecure(int el2_unused) { #if IMAGE_BL32 +#if ENABLE_AMU + amu_enable(el2_unused); +#endif #endif } diff --git a/lib/extensions/amu/aarch32/amu.c b/lib/extensions/amu/aarch32/amu.c new file mode 100644 index 00000000..d450bd69 --- /dev/null +++ b/lib/extensions/amu/aarch32/amu.c @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <amu.h> +#include <arch.h> +#include <arch_helpers.h> + +void amu_enable(int el2_unused) +{ + uint64_t features; + + features = read_id_pfr0() >> ID_PFR0_AMU_SHIFT; + if ((features & ID_PFR0_AMU_MASK) == 1) { + if (el2_unused) { + uint64_t v; + + /* + * Non-secure access from EL0 or EL1 to the Activity Monitor + * registers do not trap to EL2. + */ + v = read_hcptr(); + v &= ~TAM_BIT; + write_hcptr(v); + } + + /* Enable group 0 counters */ + write_amcntenset0(AMU_GROUP0_COUNTERS_MASK); + } +} |