diff options
author | Artsem Artsemenka <artsem.artsemenka@arm.com> | 2019-09-16 15:11:21 +0100 |
---|---|---|
committer | Artsem Artsemenka <artsem.artsemenka@arm.com> | 2019-09-30 12:55:31 +0100 |
commit | a4668c36f1fca75bce99cb706ba7c27e0c16454d (patch) | |
tree | 4dd7fd7ce3004d9edc775f8ec81a3830ea47632d /lib | |
parent | ace23683beb81354d6edbc61c087ab8c384d0631 (diff) |
Cortex_hercules: Add support for Hercules-AE
Not tested on FVP Model.
Change-Id: Iedebc5c1fbc7ea577e94142b7feafa5546f1f4f9
Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
Diffstat (limited to 'lib')
-rw-r--r-- | lib/cpus/aarch64/cortex_hercules_ae.S | 100 |
1 files changed, 100 insertions, 0 deletions
diff --git a/lib/cpus/aarch64/cortex_hercules_ae.S b/lib/cpus/aarch64/cortex_hercules_ae.S new file mode 100644 index 00000000..c4a21635 --- /dev/null +++ b/lib/cpus/aarch64/cortex_hercules_ae.S @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2019, ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <common/bl_common.h> +#include <cortex_hercules_ae.h> +#include <cpu_macros.S> +#include <plat_macros.S> + +/* Hardware handled coherency */ +#if HW_ASSISTED_COHERENCY == 0 +#error "cortex_hercules_ae must be compiled with HW_ASSISTED_COHERENCY enabled" +#endif + + /* ------------------------------------------------- + * The CPU Ops reset function for Cortex-Hercules-AE + * ------------------------------------------------- + */ +#if ENABLE_AMU +func cortex_hercules_ae_reset_func + /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ + mrs x0, actlr_el3 + bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT + msr actlr_el3, x0 + + /* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */ + mrs x0, actlr_el2 + bic x0, x0, #CORTEX_HERCULES_ACTLR_TAM_BIT + msr actlr_el2, x0 + + /* Enable group0 counters */ + mov x0, #CORTEX_HERCULES_AMU_GROUP0_MASK + msr CPUAMCNTENSET0_EL0, x0 + + /* Enable group1 counters */ + mov x0, #CORTEX_HERCULES_AMU_GROUP1_MASK + msr CPUAMCNTENSET1_EL0, x0 + isb + + ret +endfunc cortex_hercules_ae_reset_func +#endif + + /* ------------------------------------------------------- + * HW will do the cache maintenance while powering down + * ------------------------------------------------------- + */ +func cortex_hercules_ae_core_pwr_dwn + /* ------------------------------------------------------- + * Enable CPU power down bit in power control register + * ------------------------------------------------------- + */ + mrs x0, CORTEX_HERCULES_CPUPWRCTLR_EL1 + orr x0, x0, #CORTEX_HERCULES_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT + msr CORTEX_HERCULES_CPUPWRCTLR_EL1, x0 + isb + ret +endfunc cortex_hercules_ae_core_pwr_dwn + + /* + * Errata printing function for cortex_hercules_ae. Must follow AAPCS. + */ +#if REPORT_ERRATA +func cortex_hercules_ae_errata_report + ret +endfunc cortex_hercules_ae_errata_report +#endif + + /* ------------------------------------------------------- + * This function provides cortex_hercules_ae specific + * register information for crash reporting. + * It needs to return with x6 pointing to + * a list of register names in ascii and + * x8 - x15 having values of registers to be + * reported. + * ------------------------------------------------------- + */ +.section .rodata.cortex_hercules_ae_regs, "aS" +cortex_hercules_ae_regs: /* The ascii list of register names to be reported */ + .asciz "cpuectlr_el1", "" + +func cortex_hercules_ae_cpu_reg_dump + adr x6, cortex_hercules_ae_regs + mrs x8, CORTEX_HERCULES_CPUECTLR_EL1 + ret +endfunc cortex_hercules_ae_cpu_reg_dump + +#if ENABLE_AMU +#define HERCULES_AE_RESET_FUNC cortex_hercules_ae_reset_func +#else +#define HERCULES_AE_RESET_FUNC CPU_NO_RESET_FUNC +#endif + +declare_cpu_ops cortex_hercules_ae, CORTEX_HERCULES_AE_MIDR, \ + HERCULES_AE_RESET_FUNC, \ + cortex_hercules_ae_core_pwr_dwn |