diff options
author | Aymen Sghaier <aymen.sghaier@nxp.com> | 2017-11-07 15:30:35 +0100 |
---|---|---|
committer | Abel Vesa <abel.vesa@nxp.com> | 2018-06-11 10:08:40 +0300 |
commit | 15a5bfb1856a80ce89b0553259b519fac35fcf7a (patch) | |
tree | 7fe4621810e6438c4cc911e02c60ab3dacb38c7f /plat/imx/imx8mq | |
parent | e9eb91cb9374f1cba3927351033842379079495b (diff) |
imx8mq: Add csu support
Enable the CSU driver for i.MX8MQ platform with a default settings
as an example.
Signed-off-by: Aymen Sghaier <aymen.sghaier@nxp.com>
Diffstat (limited to 'plat/imx/imx8mq')
-rw-r--r-- | plat/imx/imx8mq/imx8m_bl31_setup.c | 16 | ||||
-rw-r--r-- | plat/imx/imx8mq/imx_csu.c | 273 | ||||
-rw-r--r-- | plat/imx/imx8mq/include/imx_csu.h | 214 | ||||
-rw-r--r-- | plat/imx/imx8mq/include/platform_def.h | 1 | ||||
-rw-r--r-- | plat/imx/imx8mq/platform.mk | 1 |
5 files changed, 499 insertions, 6 deletions
diff --git a/plat/imx/imx8mq/imx8m_bl31_setup.c b/plat/imx/imx8mq/imx8m_bl31_setup.c index 176283c0..5b5bef59 100644 --- a/plat/imx/imx8mq/imx8m_bl31_setup.c +++ b/plat/imx/imx8mq/imx8m_bl31_setup.c @@ -44,6 +44,7 @@ #include <xlat_tables.h> #include <soc.h> #include <tzc380.h> +#include <imx_csu.h> /* linker defined symbols */ #if USE_COHERENT_MEM @@ -58,6 +59,14 @@ static entry_point_info_t bl32_image_ep_info; static entry_point_info_t bl33_image_ep_info; +static void bl31_imx_csu_setup(void) +{ + NOTICE("Configuring CSU slaves ... \n"); + csu_set_default_slaves_modes(); + NOTICE("Configuring CSU secure access ... \n"); + csu_set_default_secure_configs(); +} + /* get SPSR for BL33 entry */ static uint32_t get_spsr_for_bl33_entry(void) { @@ -127,12 +136,6 @@ void bl31_tzc380_setup(void) void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { - int i; - /* enable CSU NS access permission */ - for (i = 0; i < 64; i++) { - mmio_write_32(0x303e0000 + i * 4, 0xffffffff); - } - /* config the AIPSTZ1 */ mmio_write_32(0x301f0000, 0x77777777); mmio_write_32(0x301f0004, 0x77777777); @@ -195,6 +198,7 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, bl33_image_ep_info.args.arg2 = 0x2000000; #endif bl31_tzc380_setup(); + bl31_imx_csu_setup(); } void bl31_plat_arch_setup(void) diff --git a/plat/imx/imx8mq/imx_csu.c b/plat/imx/imx8mq/imx_csu.c new file mode 100644 index 00000000..194644c1 --- /dev/null +++ b/plat/imx/imx8mq/imx_csu.c @@ -0,0 +1,273 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <debug.h> +#include <stdlib.h> +#include <stdint.h> +#include <platform_def.h> +#include <utils_def.h> +#include <mmio.h> +#include <imx_csu.h> + +#define CSU_HP0_OFFSET (0x200) +#define CSU_HP1_OFFSET (0x204) +#define CSU_SA_OFFSET (0x218) +#define CSU_HPC0_OFFSET (0x358) +#define CSU_HPC1_OFFSET (0x35C) + + +/* Default CSU slaves CSLn settings */ +static struct csu_slave_conf csu_def_csl_conf[] = { + {CSU_CSLn_GPIO1, CSU_RW, 0}, + {CSU_CSLn_GPIO2, CSU_RW, 0}, + {CSU_CSLn_GPIO3, CSU_RW, 0}, + {CSU_CSLn_GPIO4, CSU_RW, 0}, + {CSU_CSLn_GPIO5, CSU_RW, 0}, + {CSU_CSLn_ANA_TSENSOR, CSU_RW, 0}, + {CSU_CSLn_ANA_OSC, CSU_RW, 0}, + {CSU_CSLn_WDOG1, CSU_RW, 0}, + {CSU_CSLn_WDOG2, CSU_RW, 0}, + {CSU_CSLn_WDOG3, CSU_RW, 0}, + {CSU_CSLn_SDMA2, CSU_RW, 0}, + {CSU_CSLn_GPT1, CSU_RW, 0}, + {CSU_CSLn_GPT2, CSU_RW, 0}, + {CSU_CSLn_GPT3, CSU_RW, 0}, + {CSU_CSLn_ROMCP, CSU_RW, 0}, + {CSU_CSLn_LCDIF, CSU_RW, 0}, + {CSU_CSLn_IOMUXC, CSU_RW, 0}, + {CSU_CSLn_IOMUXC_GPR, CSU_RW, 0}, + {CSU_CSLn_OCOTP_CTRL, CSU_RW, 0}, + {CSU_CSLn_ANATOP_PLL, CSU_RW, 0}, + {CSU_CSLn_SNVS_HP, CSU_RW, 0}, + {CSU_CSLn_CCM, CSU_RW, 0}, + {CSU_CSLn_SRC, CSU_RW, 0}, + {CSU_CSLn_GPC, CSU_RW, 0}, + {CSU_CSLn_SEMAPHORE1, CSU_RW, 0}, + {CSU_CSLn_SEMAPHORE2, CSU_RW, 0}, + {CSU_CSLn_RDC, CSU_RW, 0}, + {CSU_CSLn_CSU, CSU_RW, 0}, + {CSU_CSLn_MST0, CSU_RW, 0}, + {CSU_CSLn_MST1, CSU_RW, 0}, + {CSU_CSLn_MST2, CSU_RW, 0}, + {CSU_CSLn_MST3, CSU_RW, 0}, + {CSU_CSLn_HDMI_SEC, CSU_RW, 0}, + {CSU_CSLn_PWM1, CSU_RW, 0}, + {CSU_CSLn_PWM2, CSU_RW, 0}, + {CSU_CSLn_PWM3, CSU_RW, 0}, + {CSU_CSLn_PWM4, CSU_RW, 0}, + {CSU_CSLn_SysCounter_RD, CSU_RW, 0}, + {CSU_CSLn_SysCounter_CMP, CSU_RW, 0}, + {CSU_CSLn_SysCounter_CTRL, CSU_RW, 0}, + {CSU_CSLn_HDMI_CTRL, CSU_RW, 0}, + {CSU_CSLn_GPT6, CSU_RW, 0}, + {CSU_CSLn_GPT5, CSU_RW, 0}, + {CSU_CSLn_GPT4, CSU_RW, 0}, + {CSU_CSLn_TZASC, CSU_RW, 0}, + {CSU_CSLn_MTR, CSU_RW, 0}, + {CSU_CSLn_PERFMON1, CSU_RW, 0}, + {CSU_CSLn_PERFMON2, CSU_RW, 0}, + {CSU_CSLn_PLATFORM_CTRL, CSU_RW, 0}, + {CSU_CSLn_QoSC, CSU_RW, 0}, + {CSU_CSLn_MIPI_PHY, CSU_RW, 0}, + {CSU_CSLn_MIPI_DSI, CSU_RW, 0}, + {CSU_CSLn_I2C1, CSU_RW, 0}, + {CSU_CSLn_I2C2, CSU_RW, 0}, + {CSU_CSLn_I2C3, CSU_RW, 0}, + {CSU_CSLn_I2C4, CSU_RW, 0}, + {CSU_CSLn_UART4, CSU_RW, 0}, + {CSU_CSLn_MIPI_CSI1, CSU_RW, 0}, + {CSU_CSLn_MIPI_CSI_PHY1, CSU_RW, 0}, + {CSU_CSLn_CSI1, CSU_RW, 0}, + {CSU_CSLn_MU_A, CSU_RW, 0}, + {CSU_CSLn_MU_B, CSU_RW, 0}, + {CSU_CSLn_SEMAPHORE_HS, CSU_RW, 0}, + {CSU_CSLn_SAI1, CSU_RW, 0}, + {CSU_CSLn_SAI6, CSU_RW, 0}, + {CSU_CSLn_SAI5, CSU_RW, 0}, + {CSU_CSLn_SAI4, CSU_RW, 0}, + {CSU_CSLn_USDHC1, CSU_RW, 0}, + {CSU_CSLn_USDHC2, CSU_RW, 0}, + {CSU_CSLn_MIPI_CSI2, CSU_RW, 0}, + {CSU_CSLn_MIPI_CSI_PHY2, CSU_RW, 0}, + {CSU_CSLn_CSI2, CSU_RW, 0}, + {CSU_CSLn_QSPI, CSU_RW, 0}, + {CSU_CSLn_SDMA1, CSU_RW, 0}, + {CSU_CSLn_ENET1, CSU_RW, 0}, + {CSU_CSLn_SPDIF1, CSU_RW, 0}, + {CSU_CSLn_ECSPI1, CSU_RW, 0}, + {CSU_CSLn_ECSPI2, CSU_RW, 0}, + {CSU_CSLn_ECSPI3, CSU_RW, 0}, + {CSU_CSLn_UART1, CSU_RW, 0}, + {CSU_CSLn_UART3, CSU_RW, 0}, + {CSU_CSLn_UART2, CSU_RW, 0}, + {CSU_CSLn_SPDIF2, CSU_RW, 0}, + {CSU_CSLn_SAI2, CSU_RW, 0}, + {CSU_CSLn_SAI3, CSU_RW, 0}, + {CSU_CSLn_SPBA1, CSU_RW, 0}, + {CSU_CSLn_MOD_EN3, CSU_RW, 0}, + {CSU_CSLn_MOD_EN0, CSU_RW, 0}, + {CSU_CSLn_CAAM, CSU_RW, 0}, + {CSU_CSLn_DDRC_SEC, CSU_RW, 0}, + {CSU_CSLn_GIC_EXSC, CSU_RW, 0}, + {CSU_CSLn_USB_EXSC, CSU_RW, 0}, + {CSU_CSLn_OCRAM_TZ, CSU_RW, 0}, + {CSU_CSLn_OCRAM_S_TZ, CSU_RW, 0}, + {CSU_CSLn_VPU_SEC, CSU_RW, 0}, + {CSU_CSLn_DAP_EXSC, CSU_RW, 0}, + {CSU_CSLn_ROMCP_SEC, CSU_RW, 0}, + {CSU_CSLn_APBHDMA_SEC, CSU_RW, 0}, + {CSU_CSLn_M4_SEC, CSU_RW, 0}, + {CSU_CSLn_QSPI_SEC, CSU_RW, 0}, + {CSU_CSLn_GPU_EXSC, CSU_RW, 0}, + {CSU_CSLn_Internal1, CSU_RW, 0}, + {CSU_CSLn_Internal2, CSU_RW, 0}, + {CSU_CSLn_Internal3, CSU_RW, 0}, + {CSU_CSLn_Internal4, CSU_RW, 0}, + {CSU_CSLn_Internal5, CSU_RW, 0}, + {CSU_CSLn_Internal6, CSU_RW, 0}, +}; + +/* Default Secure Access configuration */ +static struct csu_sa_conf sa_def_configs[] = { + {CSU_SA_VPU, 1, 1}, + {CSU_SA_GPU, 1, 1}, + {CSU_SA_DCSS, 1, 1}, +}; + +void csu_set_slave_index_mode(enum csu_csln_idx index, + uint16_t mode, uint8_t lock) +{ + uintptr_t reg; + uint32_t tmp; + uint16_t read_mode; + uint8_t read_lock = 0; + + /* Check if CSLn is locked or the value is same as written */ + csu_get_slave_index_mode(index, &read_mode, &read_lock); + if (read_lock) { + NOTICE("CSU CSLn(%d) already locked with mode:0x%x\n", index, read_mode); + return; + } + if (read_mode == mode && lock == 0) { + NOTICE("CSU CSLn(%d) mode 0x%x already written\n", index, read_mode); + return; + } + reg = (uintptr_t)(IMX_CSU_BASE + (index / 2) * 4); + tmp = mmio_read_32(reg); + if (index % 2 == 0) { + tmp &= 0x0000ffff; + tmp |= mode << 16 | lock << 24; + } else { + tmp &= 0xffff0000; + tmp |= mode | lock << 8; + } + mmio_write_32(reg, tmp); +} + +void csu_get_slave_index_mode(enum csu_csln_idx index, + uint16_t *mode, uint8_t *lock) +{ + uintptr_t reg; + uint32_t tmp; + + reg = (uintptr_t)(IMX_CSU_BASE + (index / 2) * 4); + tmp = mmio_read_32(reg); + if (index % 2 == 0) { + *mode = (uint16_t)(tmp >> 16 & 0xff); + *lock = (uint8_t)(tmp >> 24 & 0x01); + } else { + *mode = (uint16_t)(tmp & 0xff); + *lock = (uint8_t)(tmp >> 8 & 0x01); + } +} + +void csu_set_slaves_modes(struct csu_slave_conf *csu_config, uint32_t count) +{ + int i; + + for (i = 0; i < count; i++) { + csu_set_slave_index_mode(csu_config[i].index, csu_config[i].mode, csu_config[i].lock); + } +} + +void csu_set_default_slaves_modes(void) +{ + NOTICE("csu_set_default_slaves_modes: count = %d \n", (int)ARRAY_SIZE(csu_def_csl_conf)); + csu_set_slaves_modes(csu_def_csl_conf, (uint32_t)ARRAY_SIZE(csu_def_csl_conf)); +} + +void csu_set_hp_index_config(enum csu_hp_idx index, uint8_t enable, + uint8_t set_control, uint8_t lock) +{ + uint32_t tmp, value; + uintptr_t reg; + + if (index < 16){ + reg = (uintptr_t)(IMX_CSU_BASE + CSU_HP0_OFFSET); + tmp = mmio_read_32(reg); + value = 0x3 << (index * 2); + tmp &= ~value; + value = (lock * 2 | enable) << (index * 2); + tmp |= value; + mmio_write_32(reg, tmp); + if (set_control) { + reg = (uintptr_t)(IMX_CSU_BASE + CSU_HPC0_OFFSET); + tmp = mmio_read_32(reg); + value = (lock * 2 | set_control) << (index * 2); + tmp &= ~value; + tmp |= value; + mmio_write_32(reg, tmp); + } + } else { + reg = (uintptr_t)(IMX_CSU_BASE + CSU_HP1_OFFSET); + mmio_write_32(reg,lock * 2 | enable); + if (set_control) { + reg = (uintptr_t)(IMX_CSU_BASE + CSU_HPC1_OFFSET); + mmio_write_32(reg,lock * 2 | set_control); + } + } +} + +void csu_set_sa_index_config(enum csu_sa_idx index, + uint8_t enable, uint8_t lock) +{ + uint32_t tmp, value; + uintptr_t reg; + + reg = (uintptr_t)(IMX_CSU_BASE + CSU_SA_OFFSET); + tmp = mmio_read_32((uintptr_t)reg); + value = 0x3 << (index * 2); + tmp &= ~value; + value = (lock * 2 | enable) << (index * 2); + tmp |= value; + mmio_write_32(reg, tmp); +} + +void csu_get_sa_index_config(enum csu_sa_idx index, + uint8_t *enable, uint8_t *lock) +{ + uint32_t tmp; + uintptr_t reg; + + reg = (uintptr_t)(IMX_CSU_BASE + CSU_SA_OFFSET); + tmp = mmio_read_32((uintptr_t)reg); + *enable = (tmp >> (index * 2)) & 1; + *lock = (tmp >> (index * 2 + 1)) & 1; +} + +void csu_set_sa_configs(struct csu_sa_conf *sa_conf, uint32_t count) +{ + int i; + + for (i = 0; i < count; i++) + csu_set_sa_index_config(sa_conf[i].index, + sa_conf[i].enable, sa_conf[i].lock); +} + +void csu_set_default_secure_configs(void) +{ + csu_set_sa_configs(sa_def_configs, (uint32_t)ARRAY_SIZE(sa_def_configs)); +} diff --git a/plat/imx/imx8mq/include/imx_csu.h b/plat/imx/imx8mq/include/imx_csu.h new file mode 100644 index 00000000..c5a198c9 --- /dev/null +++ b/plat/imx/imx8mq/include/imx_csu.h @@ -0,0 +1,214 @@ +/* + * Copyright 2017 NXP + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __IMX_CSU_H__ +#define __IMX_CSU_H__ + +enum csu_mode { + CSU_NSR = 0x08, + CSU_NSW = 0x80, + CSU_NSRW = 0x88, + CSU_NUR = 0x04, + CSU_NUW = 0x40, + CSU_NURW = 0x44, + CSU_SSR = 0x02, + CSU_SSW = 0x20, + CSU_SSRW = 0x22, + CSU_SUR = 0x01, + CSU_SUW = 0x10, + CSU_SURW = 0x11, + CSU_RW = 0xff, +}; + +enum csu_csln_idx { + CSU_CSLn_GPIO1 = 0, + CSU_CSLn_GPIO2 = 1, + CSU_CSLn_GPIO3 = 2, + CSU_CSLn_GPIO4 = 3, + CSU_CSLn_GPIO5 = 4, + CSU_CSLn_Reserved1 = 5, + CSU_CSLn_ANA_TSENSOR = 6, + CSU_CSLn_ANA_OSC = 7, + CSU_CSLn_WDOG1 = 8, + CSU_CSLn_WDOG2 = 9, + CSU_CSLn_WDOG3 = 10, + CSU_CSLn_Reserved2 = 11, + CSU_CSLn_SDMA2 = 12, + CSU_CSLn_GPT1 = 13, + CSU_CSLn_GPT2 = 14, + CSU_CSLn_GPT3 = 15, + CSU_CSLn_Reserved3 = 16, + CSU_CSLn_ROMCP = 17, + CSU_CSLn_LCDIF = 18, + CSU_CSLn_IOMUXC = 19, + CSU_CSLn_IOMUXC_GPR = 20, + CSU_CSLn_OCOTP_CTRL = 21, + CSU_CSLn_ANATOP_PLL = 22, + CSU_CSLn_SNVS_HP = 23, + CSU_CSLn_CCM = 24, + CSU_CSLn_SRC = 25, + CSU_CSLn_GPC = 26, + CSU_CSLn_SEMAPHORE1 = 27, + CSU_CSLn_SEMAPHORE2 = 28, + CSU_CSLn_RDC = 29, + CSU_CSLn_CSU = 30, + CSU_CSLn_Reserved4 = 31, + CSU_CSLn_MST0 = 32, + CSU_CSLn_MST1 = 33, + CSU_CSLn_MST2 = 34, + CSU_CSLn_MST3 = 35, + CSU_CSLn_HDMI_SEC = 36, + CSU_CSLn_Reserved5 = 37, + CSU_CSLn_PWM1 = 38, + CSU_CSLn_PWM2 = 39, + CSU_CSLn_PWM3 = 40, + CSU_CSLn_PWM4 = 41, + CSU_CSLn_SysCounter_RD = 42, + CSU_CSLn_SysCounter_CMP = 43, + CSU_CSLn_SysCounter_CTRL = 44, + CSU_CSLn_HDMI_CTRL = 45, + CSU_CSLn_GPT6 = 46, + CSU_CSLn_GPT5 = 47, + CSU_CSLn_GPT4 = 48, + CSU_CSLn_TZASC = 56, + CSU_CSLn_MTR = 59, + CSU_CSLn_PERFMON1 = 60, + CSU_CSLn_PERFMON2 = 61, + CSU_CSLn_PLATFORM_CTRL = 62, + CSU_CSLn_QoSC = 63, + CSU_CSLn_MIPI_PHY = 64, + CSU_CSLn_MIPI_DSI = 65, + CSU_CSLn_I2C1 = 66, + CSU_CSLn_I2C2 = 67, + CSU_CSLn_I2C3 = 68, + CSU_CSLn_I2C4 = 69, + CSU_CSLn_UART4 = 70, + CSU_CSLn_MIPI_CSI1 = 71, + CSU_CSLn_MIPI_CSI_PHY1 = 72, + CSU_CSLn_CSI1 = 73, + CSU_CSLn_MU_A = 74, + CSU_CSLn_MU_B = 75, + CSU_CSLn_SEMAPHORE_HS = 76, + CSU_CSLn_Internal1 = 77, + CSU_CSLn_SAI1 = 78, + CSU_CSLn_Reserved7 = 79, + CSU_CSLn_SAI6 = 80, + CSU_CSLn_SAI5 = 81, + CSU_CSLn_SAI4 = 82, + CSU_CSLn_Internal2 = 83, + CSU_CSLn_USDHC1 = 84, + CSU_CSLn_USDHC2 = 85, + CSU_CSLn_MIPI_CSI2 = 86, + CSU_CSLn_MIPI_CSI_PHY2 = 87, + CSU_CSLn_CSI2 = 88, + CSU_CSLn_Internal3 = 89, + CSU_CSLn_Reserved10 = 90, + CSU_CSLn_QSPI = 91, + CSU_CSLn_Reserved11 = 92, + CSU_CSLn_SDMA1 = 93, + CSU_CSLn_ENET1 = 94, + CSU_CSLn_Reserved12 = 95, + CSU_CSLn_Internal4 = 96, + CSU_CSLn_SPDIF1 = 97, + CSU_CSLn_ECSPI1 = 98, + CSU_CSLn_ECSPI2 = 99, + CSU_CSLn_ECSPI3 = 100, + CSU_CSLn_Reserved14 = 101, + CSU_CSLn_UART1 = 102, + CSU_CSLn_Internal5 = 103, + CSU_CSLn_UART3 = 104, + CSU_CSLn_UART2 = 105, + CSU_CSLn_SPDIF2 = 106, + CSU_CSLn_SAI2 = 107, + CSU_CSLn_SAI3 = 108, + CSU_CSLn_Reserved16 = 109, + CSU_CSLn_Internal6 = 110, + CSU_CSLn_SPBA1 = 111, + CSU_CSLn_MOD_EN3 = 112, + CSU_CSLn_MOD_EN0 = 113, + CSU_CSLn_CAAM = 114, + CSU_CSLn_DDRC_SEC = 115, + CSU_CSLn_GIC_EXSC = 116, + CSU_CSLn_USB_EXSC = 117, + CSU_CSLn_OCRAM_TZ = 118, + CSU_CSLn_OCRAM_S_TZ = 119, + CSU_CSLn_VPU_SEC = 120, + CSU_CSLn_DAP_EXSC = 121, + CSU_CSLn_ROMCP_SEC = 122, + CSU_CSLn_APBHDMA_SEC = 123, + CSU_CSLn_M4_SEC = 124, + CSU_CSLn_QSPI_SEC = 125, + CSU_CSLn_GPU_EXSC = 126, + CSU_CSLn_PCIE = 127, +}; + +enum csu_hp_idx { + CSU_HP_A53, + CSU_HP_M4, + CSU_HP_SDMA1, + CSU_HP_CSI, + CSU_HP_USB, + CSU_HP_PCIE, + CSU_HP_VPU, + CSU_HP_GPU, + CSU_HP_APBHDMA, + CSU_HP_ENET, + CSU_HP_USDHC1, + CSU_HP_USDHC2, + CSU_HP_DCSS, + CSU_HP_HUGO, + CSU_HP_DAP, + CSU_HP_SDMA2, + CSU_HP_CAAM, +}; + +enum csu_sa_idx { + CSU_SA_M4, + CSU_SA_SDMA1, + CSU_SA_CSI, + CSU_SA_USB, + CSU_SA_PCIE, + CSU_SA_VPU, + CSU_SA_GPU, + CSU_SA_APBHDMA, + CSU_SA_ENET, + CSU_SA_USDHC1, + CSU_SA_USDHC2, + CSU_SA_DCSS, + CSU_SA_HUGO, + CSU_SA_DAP, + CSU_SA_SDMA2, + CSU_SA_CAAM, +}; + +struct csu_slave_conf { + enum csu_csln_idx index; + uint16_t mode; + uint16_t lock; +}; + +struct csu_sa_conf { + enum csu_sa_idx index; + uint8_t enable; + uint8_t lock; +}; + +void csu_set_slave_index_mode(enum csu_csln_idx index, + uint16_t mode, uint8_t lock); +void csu_get_slave_index_mode(enum csu_csln_idx index, + uint16_t *mode, uint8_t *lock); +void csu_set_slaves_modes(struct csu_slave_conf *csu_config, uint32_t count); +void csu_set_default_slaves_modes(void); +void csu_set_hp_index_config(enum csu_hp_idx index, uint8_t enable, + uint8_t set_control, uint8_t lock); +void csu_set_sa_index_config(enum csu_sa_idx index, uint8_t enable, + uint8_t lock); +void csu_get_sa_index_config(enum csu_sa_idx index, uint8_t *enable, + uint8_t *lock); +void csu_set_sa_configs(struct csu_sa_conf *sa_configs, uint32_t count); +void csu_set_default_secure_configs(void); + +#endif /* __IMX_CSU_H__ */ diff --git a/plat/imx/imx8mq/include/platform_def.h b/plat/imx/imx8mq/include/platform_def.h index 30fcf5a3..222bc1cc 100644 --- a/plat/imx/imx8mq/include/platform_def.h +++ b/plat/imx/imx8mq/include/platform_def.h @@ -50,6 +50,7 @@ #define IMX_ANAMIX_BASE 0x30360000 #define IMX_SRC_BASE 0x30390000 #define IMX_GPC_BASE 0x303a0000 +#define IMX_CSU_BASE 0x303e0000 #define IMX_WDOG_BASE 0x30280000 #define IMX_SNVS_BASE 0x30370000 #define IMX_TZASC_BASE 0x32F80000 diff --git a/plat/imx/imx8mq/platform.mk b/plat/imx/imx8mq/platform.mk index 16114123..c1f5a220 100644 --- a/plat/imx/imx8mq/platform.mk +++ b/plat/imx/imx8mq/platform.mk @@ -15,6 +15,7 @@ BL31_SOURCES += plat/imx/common/imx8_helpers.S \ plat/imx/imx8mq/gpc.c \ plat/imx/imx8mq/ddrc.c \ plat/imx/imx8mq/imx8m_psci.c \ + plat/imx/imx8mq/imx_csu.c \ plat/imx/common/imx8_topology.c \ plat/common/plat_psci_common.c \ lib/xlat_tables/aarch64/xlat_tables.c \ |