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authorBai Ping <ping.bai@nxp.com>2017-12-06 13:41:02 +0800
committerAbel Vesa <abel.vesa@nxp.com>2018-06-11 10:33:02 +0300
commit66b28ef7fd902017bffeaae4fafffa430c516557 (patch)
tree7523751fd9fee8314e47c22c7785fdf5812700da /plat/imx/imx8mq
parent82beeec96ad2d271881c9e97dcd5c7b57e7df3c8 (diff)
plat: imx: Update the DDR performance setting
Update the DDR performance setting when out of retention. Signed-off-by: Bai Ping <ping.bai@nxp.com>
Diffstat (limited to 'plat/imx/imx8mq')
-rw-r--r--plat/imx/imx8mq/ddrc.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/plat/imx/imx8mq/ddrc.c b/plat/imx/imx8mq/ddrc.c
index 2557d2b2..40dec4c5 100644
--- a/plat/imx/imx8mq/ddrc.c
+++ b/plat/imx/imx8mq/ddrc.c
@@ -2566,7 +2566,7 @@ void lpddr4_cfg_umctl2(void)
mmio_write_32(IMX_DDRC_BASE + DDRC_SCHED, 0x29511505);
mmio_write_32(IMX_DDRC_BASE + DDRC_SCHED1, 0x0000002c);
mmio_write_32(IMX_DDRC_BASE + DDRC_PERFHPR1, 0x5900575b);
- mmio_write_32(IMX_DDRC_BASE + DDRC_PERFLPR1, 0x900093e7);
+ mmio_write_32(IMX_DDRC_BASE + DDRC_PERFLPR1, 0x00000009);
mmio_write_32(IMX_DDRC_BASE + DDRC_PERFWR1, 0x02005574);
mmio_write_32(IMX_DDRC_BASE + DDRC_DBG0, 0x00000016);
mmio_write_32(IMX_DDRC_BASE + DDRC_DBG1, 0x00000000);