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authorBai Ping <ping.bai@nxp.com>2018-03-02 13:14:00 +0800
committerAbel Vesa <abel.vesa@nxp.com>2018-06-11 10:33:02 +0300
commit02cba32824185a28605130e7a7ae6dd79f3e4fa6 (patch)
tree96ae0d40ff5551404f7ce239c019ca366ff904b7 /plat
parentf2c72a59cf9797e065fdb4635f5cd5a9a861fc3c (diff)
plat: imx8mq: fix boot hang on ddr4/ddr3l board
Currently, DDR3L/DDR4 board don't support DDR DVFS, So skip ddr switch 3200 mts if the DDR is not LPDDR4. Signed-off-by: Bai Ping <ping.bai@nxp.com>
Diffstat (limited to 'plat')
-rw-r--r--plat/imx/imx8mq/ddr/lpddr4_dvfs.c11
1 files changed, 10 insertions, 1 deletions
diff --git a/plat/imx/imx8mq/ddr/lpddr4_dvfs.c b/plat/imx/imx8mq/ddr/lpddr4_dvfs.c
index 8f37fc7d..bd96bbac 100644
--- a/plat/imx/imx8mq/ddr/lpddr4_dvfs.c
+++ b/plat/imx/imx8mq/ddr/lpddr4_dvfs.c
@@ -17,6 +17,9 @@
#include "lpddr4_dvfs.h"
+#define DDRC_LPDDR4 (1 << 5)
+#define DDR_TYPE_MASK 0x3f
+
/* lock used for DDR DVFS */
spinlock_t dfs_lock;
/* IRQ used for DDR DVFS */
@@ -26,9 +29,15 @@ static volatile bool wait_ddrc_hwffc_done = true;
static unsigned int init_fsp = 0x1;
+static inline int get_ddr_type(void)
+{
+ return mmio_read_32(IMX_DDRC_BASE + DDRC_MSTR(0)) & DDR_TYPE_MASK;
+}
+
void lpddr4_switch_to_3200(void)
{
- lpddr4_dvfs_swffc(init_fsp, 0x0);
+ if (get_ddr_type() == DDRC_LPDDR4)
+ lpddr4_dvfs_swffc(init_fsp, 0x0);
}
/*