summaryrefslogtreecommitdiff
path: root/plat
diff options
context:
space:
mode:
authorFranck LENORMAND <franck.lenormand@nxp.com>2018-01-23 15:04:08 +0100
committerAbel Vesa <abel.vesa@nxp.com>2018-06-11 10:33:02 +0300
commit0ad3ae282a59466ea08783aeefcb39a762f453ba (patch)
treed0f42d779b6f6aab7519195947ddb9cbdad102d0 /plat
parentf069dc365b0ba85ee0f83bef26ae54b11b2fdc7b (diff)
MLK-17253: Initialize caam sm at boot
At boot, we reset the Secure Memory configuration for imx8mq to a default state giving all the job rings to linux and allowing all accesses from all SDIDs. NOTE: Checkpatch OK. Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
Diffstat (limited to 'plat')
-rw-r--r--plat/imx/imx8mq/imx8m_bl31_setup.c40
1 files changed, 40 insertions, 0 deletions
diff --git a/plat/imx/imx8mq/imx8m_bl31_setup.c b/plat/imx/imx8mq/imx8m_bl31_setup.c
index 8e718d61..98f25816 100644
--- a/plat/imx/imx8mq/imx8m_bl31_setup.c
+++ b/plat/imx/imx8mq/imx8m_bl31_setup.c
@@ -57,11 +57,27 @@
#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
#define BL31_END (unsigned long)(&__BL31_END__)
+#define CAAM_BASE (0x30900000) /* HW address*/
+
+#define JR0_BASE (CAAM_BASE + 0x1000)
+
#define CAAM_JR0MID (0x30900010)
#define CAAM_JR1MID (0x30900018)
#define CAAM_JR2MID (0x30900020)
#define CAAM_NS_MID (0x1)
+#define SM_P0_PERM (JR0_BASE + 0xa04)
+#define SM_P0_SMAG2 (JR0_BASE + 0xa08)
+#define SM_P0_SMAG1 (JR0_BASE + 0xa0c)
+#define SM_CMD (JR0_BASE + 0xbe4)
+
+/* secure memory command */
+#define SMC_PAGE_SHIFT 16
+#define SMC_PART_SHIFT 8
+
+#define SMC_CMD_ALLOC_PAGE 0x01 /* allocate page to this partition */
+#define SMC_CMD_DEALLOC_PART 0x03 /* deallocate partition */
+
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
@@ -135,11 +151,19 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
int i;
+ uint32_t sm_cmd;
/* enable CSU NS access permission */
for (i = 0; i < 64; i++) {
mmio_write_32(0x303e0000 + i * 4, 0xffffffff);
}
+ /* Dealloc part 0 and 2 with current DID */
+ sm_cmd = (0 << SMC_PART_SHIFT | SMC_CMD_DEALLOC_PART);
+ mmio_write_32(SM_CMD, sm_cmd);
+
+ sm_cmd = (2 << SMC_PART_SHIFT | SMC_CMD_DEALLOC_PART);
+ mmio_write_32(SM_CMD, sm_cmd);
+
/* config CAAM JRaMID set MID to Cortex A */
mmio_write_32(CAAM_JR0MID, CAAM_NS_MID);
mmio_write_32(CAAM_JR1MID, CAAM_NS_MID);
@@ -188,6 +212,22 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
/* enable the system counter */
system_counter_init();
+ /* Alloc partition 0 writing SMPO and SMAGs */
+ mmio_write_32(SM_P0_PERM, 0xff);
+ mmio_write_32(SM_P0_SMAG2, 0xffffffff);
+ mmio_write_32(SM_P0_SMAG1, 0xffffffff);
+
+ /* Allocate page 0 and 1 to partition 0 with DID set */
+ sm_cmd = (0 << SMC_PAGE_SHIFT
+ | 0 << SMC_PART_SHIFT
+ | SMC_CMD_ALLOC_PAGE);
+ mmio_write_32(SM_CMD, sm_cmd);
+
+ sm_cmd = (1 << SMC_PAGE_SHIFT
+ | 0 << SMC_PART_SHIFT
+ | SMC_CMD_ALLOC_PAGE);
+ mmio_write_32(SM_CMD, sm_cmd);
+
/*
* tell BL3-1 where the non-secure software image is located
* and the entry state information.