diff options
| -rw-r--r-- | Makefile | 6 | ||||
| -rw-r--r-- | bl1/bl1.ld.S | 38 | ||||
| -rw-r--r-- | bl2/bl2.ld.S | 25 | ||||
| -rw-r--r-- | bl2u/bl2u.ld.S | 18 | ||||
| -rw-r--r-- | bl31/bl31.ld.S | 42 | ||||
| -rw-r--r-- | bl32/tsp/tsp.ld.S | 18 | ||||
| -rw-r--r-- | docs/firmware-design.md | 8 | ||||
| -rw-r--r-- | include/common/bl_common.h | 8 |
8 files changed, 162 insertions, 1 deletions
@@ -108,6 +108,10 @@ PL011_GENERIC_UART := 0 ENABLE_PMF := 0 # Flag to enable PSCI STATs functionality ENABLE_PSCI_STAT := 0 +# Whether code and read-only data should be put on separate memory pages. +# The platform Makefile is free to override this value. +SEPARATE_CODE_AND_RODATA := 0 + ################################################################################ # Checkpatch script options @@ -419,6 +423,7 @@ $(eval $(call assert_boolean,SPIN_ON_BL1_EXIT)) $(eval $(call assert_boolean,PL011_GENERIC_UART)) $(eval $(call assert_boolean,ENABLE_PMF)) $(eval $(call assert_boolean,ENABLE_PSCI_STAT)) +$(eval $(call assert_boolean,SEPARATE_CODE_AND_RODATA)) ################################################################################ @@ -448,6 +453,7 @@ $(eval $(call add_define,SPIN_ON_BL1_EXIT)) $(eval $(call add_define,PL011_GENERIC_UART)) $(eval $(call add_define,ENABLE_PMF)) $(eval $(call add_define,ENABLE_PSCI_STAT)) +$(eval $(call add_define,SEPARATE_CODE_AND_RODATA)) # Define the EL3_PAYLOAD_BASE flag only if it is provided. ifdef EL3_PAYLOAD_BASE $(eval $(call add_define,EL3_PAYLOAD_BASE)) diff --git a/bl1/bl1.ld.S b/bl1/bl1.ld.S index be36b4ee..b9554d15 100644 --- a/bl1/bl1.ld.S +++ b/bl1/bl1.ld.S @@ -45,6 +45,43 @@ SECTIONS ASSERT(. == ALIGN(4096), "BL1_RO_BASE address is not aligned on a page boundary.") +#if SEPARATE_CODE_AND_RODATA + .text . : { + __TEXT_START__ = .; + *bl1_entrypoint.o(.text*) + *(.text*) + *(.vectors) + . = NEXT(4096); + __TEXT_END__ = .; + } >ROM + + .rodata . : { + __RODATA_START__ = .; + *(.rodata*) + + /* Ensure 8-byte alignment for descriptors and ensure inclusion */ + . = ALIGN(8); + __PARSER_LIB_DESCS_START__ = .; + KEEP(*(.img_parser_lib_descs)) + __PARSER_LIB_DESCS_END__ = .; + + /* + * Ensure 8-byte alignment for cpu_ops so that its fields are also + * aligned. Also ensure cpu_ops inclusion. + */ + . = ALIGN(8); + __CPU_OPS_START__ = .; + KEEP(*(cpu_ops)) + __CPU_OPS_END__ = .; + + /* + * No need to pad out the .rodata section to a page boundary. Next is + * the .data section, which can mapped in ROM with the same memory + * attributes as the .rodata section. + */ + __RODATA_END__ = .; + } >ROM +#else ro . : { __RO_START__ = .; *bl1_entrypoint.o(.text*) @@ -69,6 +106,7 @@ SECTIONS *(.vectors) __RO_END__ = .; } >ROM +#endif ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, "cpu_ops not defined for this platform.") diff --git a/bl2/bl2.ld.S b/bl2/bl2.ld.S index a660bda6..fa694de2 100644 --- a/bl2/bl2.ld.S +++ b/bl2/bl2.ld.S @@ -45,6 +45,30 @@ SECTIONS ASSERT(. == ALIGN(4096), "BL2_BASE address is not aligned on a page boundary.") +#if SEPARATE_CODE_AND_RODATA + .text . : { + __TEXT_START__ = .; + *bl2_entrypoint.o(.text*) + *(.text*) + *(.vectors) + . = NEXT(4096); + __TEXT_END__ = .; + } >RAM + + .rodata . : { + __RODATA_START__ = .; + *(.rodata*) + + /* Ensure 8-byte alignment for descriptors and ensure inclusion */ + . = ALIGN(8); + __PARSER_LIB_DESCS_START__ = .; + KEEP(*(.img_parser_lib_descs)) + __PARSER_LIB_DESCS_END__ = .; + + . = NEXT(4096); + __RODATA_END__ = .; + } >RAM +#else ro . : { __RO_START__ = .; *bl2_entrypoint.o(.text*) @@ -67,6 +91,7 @@ SECTIONS . = NEXT(4096); __RO_END__ = .; } >RAM +#endif /* * Define a linker symbol to mark start of the RW memory area for this diff --git a/bl2u/bl2u.ld.S b/bl2u/bl2u.ld.S index ec120779..d72589fc 100644 --- a/bl2u/bl2u.ld.S +++ b/bl2u/bl2u.ld.S @@ -45,6 +45,23 @@ SECTIONS ASSERT(. == ALIGN(4096), "BL2U_BASE address is not aligned on a page boundary.") +#if SEPARATE_CODE_AND_RODATA + .text . : { + __TEXT_START__ = .; + *bl2u_entrypoint.o(.text*) + *(.text*) + *(.vectors) + . = NEXT(4096); + __TEXT_END__ = .; + } >RAM + + .rodata . : { + __RODATA_START__ = .; + *(.rodata*) + . = NEXT(4096); + __RODATA_END__ = .; + } >RAM +#else ro . : { __RO_START__ = .; *bl2u_entrypoint.o(.text*) @@ -61,6 +78,7 @@ SECTIONS . = NEXT(4096); __RO_END__ = .; } >RAM +#endif /* * Define a linker symbol to mark start of the RW memory area for this diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S index 33cbe4b7..743e65c4 100644 --- a/bl31/bl31.ld.S +++ b/bl31/bl31.ld.S @@ -46,6 +46,47 @@ SECTIONS ASSERT(. == ALIGN(4096), "BL31_BASE address is not aligned on a page boundary.") +#if SEPARATE_CODE_AND_RODATA + .text . : { + __TEXT_START__ = .; + *bl31_entrypoint.o(.text*) + *(.text*) + *(.vectors) + . = NEXT(4096); + __TEXT_END__ = .; + } >RAM + + .rodata . : { + __RODATA_START__ = .; + *(.rodata*) + + /* Ensure 8-byte alignment for descriptors and ensure inclusion */ + . = ALIGN(8); + __RT_SVC_DESCS_START__ = .; + KEEP(*(rt_svc_descs)) + __RT_SVC_DESCS_END__ = .; + +#if ENABLE_PMF + /* Ensure 8-byte alignment for descriptors and ensure inclusion */ + . = ALIGN(8); + __PMF_SVC_DESCS_START__ = .; + KEEP(*(pmf_svc_descs)) + __PMF_SVC_DESCS_END__ = .; +#endif /* ENABLE_PMF */ + + /* + * Ensure 8-byte alignment for cpu_ops so that its fields are also + * aligned. Also ensure cpu_ops inclusion. + */ + . = ALIGN(8); + __CPU_OPS_START__ = .; + KEEP(*(cpu_ops)) + __CPU_OPS_END__ = .; + + . = NEXT(4096); + __RODATA_END__ = .; + } >RAM +#else ro . : { __RO_START__ = .; *bl31_entrypoint.o(.text*) @@ -85,6 +126,7 @@ SECTIONS . = NEXT(4096); __RO_END__ = .; } >RAM +#endif ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__, "cpu_ops not defined for this platform.") diff --git a/bl32/tsp/tsp.ld.S b/bl32/tsp/tsp.ld.S index 9c7ed381..7e24f66d 100644 --- a/bl32/tsp/tsp.ld.S +++ b/bl32/tsp/tsp.ld.S @@ -46,6 +46,23 @@ SECTIONS ASSERT(. == ALIGN(4096), "BL32_BASE address is not aligned on a page boundary.") +#if SEPARATE_CODE_AND_RODATA + .text . : { + __TEXT_START__ = .; + *tsp_entrypoint.o(.text*) + *(.text*) + *(.vectors) + . = NEXT(4096); + __TEXT_END__ = .; + } >RAM + + .rodata . : { + __RODATA_START__ = .; + *(.rodata*) + . = NEXT(4096); + __RODATA_END__ = .; + } >RAM +#else ro . : { __RO_START__ = .; *tsp_entrypoint.o(.text*) @@ -61,6 +78,7 @@ SECTIONS . = NEXT(4096); __RO_END__ = .; } >RAM +#endif /* * Define a linker symbol to mark start of the RW memory area for this diff --git a/docs/firmware-design.md b/docs/firmware-design.md index 575a822a..b99a2838 100644 --- a/docs/firmware-design.md +++ b/docs/firmware-design.md @@ -1115,7 +1115,9 @@ All BL images share the following requirements: * The BSS section must be zero-initialised before executing any C code. * The coherent memory section (if enabled) must be zero-initialised as well. * The MMU setup code needs to know the extents of the coherent and read-only - memory regions to set the right memory attributes. + memory regions to set the right memory attributes. When + `SEPARATE_CODE_AND_RODATA=1`, it needs to know more specifically how the + read-only memory region is divided between code and data. The following linker symbols are defined for this purpose: @@ -1126,6 +1128,10 @@ The following linker symbols are defined for this purpose: * `__COHERENT_RAM_UNALIGNED_SIZE__` * `__RO_START__` * `__RO_END__` +* `__TEXT_START__` +* `__TEXT_END__` +* `__RODATA_START__` +* `__RODATA_END__` #### BL1's linker symbols diff --git a/include/common/bl_common.h b/include/common/bl_common.h index c43ad5ef..646a8172 100644 --- a/include/common/bl_common.h +++ b/include/common/bl_common.h @@ -143,8 +143,16 @@ * Declarations of linker defined symbols to help determine memory layout of * BL images */ +#if SEPARATE_CODE_AND_RODATA +extern unsigned long __TEXT_START__; +extern unsigned long __TEXT_END__; +extern unsigned long __RODATA_START__; +extern unsigned long __RODATA_END__; +#else extern unsigned long __RO_START__; extern unsigned long __RO_END__; +#endif + #if IMAGE_BL2 extern unsigned long __BL2_END__; #elif IMAGE_BL2U |