diff options
71 files changed, 1751 insertions, 723 deletions
@@ -125,7 +125,7 @@ OC := ${CROSS_COMPILE}objcopy OD := ${CROSS_COMPILE}objdump NM := ${CROSS_COMPILE}nm PP := ${CROSS_COMPILE}gcc -E -DTC ?= dtc +DTC := dtc # Use ${LD}.bfd instead if it exists (as absolute path or together with $PATH). ifneq ($(strip $(wildcard ${LD}.bfd) \ @@ -192,8 +192,8 @@ BL_COMMON_SOURCES += common/bl_common.c \ common/${ARCH}/debug.S \ lib/${ARCH}/cache_helpers.S \ lib/${ARCH}/misc_helpers.S \ + plat/common/plat_bl_common.c \ plat/common/plat_log_common.c \ - plat/common/platform_helpers_default.c \ plat/common/${ARCH}/plat_common.c \ plat/common/${ARCH}/platform_helpers.S \ ${COMPILER_RT_SRCS} \ @@ -638,9 +638,7 @@ endif # Expand build macros for the different images ifeq (${NEED_FDT},yes) -$(eval $(call MAKE_DTBS,$(BUILD_PLAT)/fdts,$(FDT_SOURCES))) -$(eval $(call MAKE_FDT)) -dtbs: $(DTBS) + $(eval $(call MAKE_DTBS,$(BUILD_PLAT)/fdts,$(FDT_SOURCES))) endif locate-checkpatch: @@ -777,7 +775,7 @@ help: @echo " distclean Remove all build artifacts for all platforms" @echo " certtool Build the Certificate generation tool" @echo " fiptool Build the Firmware Image Package (FIP) creation tool" - @echo " dtbs Build the Flattened device tree (if required for the platform)" + @echo " dtbs Build the Device Tree Blobs (if required for the platform)" @echo "" @echo "Note: most build targets require PLAT to be set to a specific platform." @echo "" diff --git a/bl1/bl1_fwu.c b/bl1/bl1_fwu.c index 07a7fc81..38780833 100644 --- a/bl1/bl1_fwu.c +++ b/bl1/bl1_fwu.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -350,6 +350,15 @@ static int bl1_fwu_image_copy(unsigned int image_id, return -ENOMEM; } + /* Allow the platform to handle pre-image load before copying */ + if (image_desc->state == IMAGE_STATE_RESET) { + if (bl1_plat_handle_pre_image_load(image_id) != 0) { + ERROR("BL1-FWU: Failure in pre-image load of image id %d\n", + image_id); + return -EPERM; + } + } + /* Everything looks sane. Go ahead and copy the block of data. */ dest_addr = image_desc->image_info.image_base + image_desc->copied_size; memcpy((void *) dest_addr, (const void *) image_src, block_size); @@ -474,6 +483,18 @@ static int bl1_fwu_image_auth(unsigned int image_id, /* Indicate that image is in authenticated state. */ image_desc->state = IMAGE_STATE_AUTHENTICATED; + /* Allow the platform to handle post-image load */ + result = bl1_plat_handle_post_image_load(image_id); + if (result != 0) { + ERROR("BL1-FWU: Failure %d in post-image load of image id %d\n", + result, image_id); + /* + * Panic here as the platform handling of post-image load is + * not correct. + */ + plat_error_handler(result); + } + /* * Flush image_info to memory so that other * secure world images can see changes. diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c index 91b5f0b1..b2e7c28c 100644 --- a/bl1/bl1_main.c +++ b/bl1/bl1_main.c @@ -25,24 +25,15 @@ DEFINE_SVC_UUID(bl1_svc_uid, 0xfd3967d4, 0x72cb, 0x4d9a, 0xb5, 0x75, 0x67, 0x15, 0xd6, 0xf4, 0xbb, 0x4a); - static void bl1_load_bl2(void); /******************************************************************************* - * The next function has a weak definition. Platform specific code can override - * it if it wishes to. - ******************************************************************************/ -#pragma weak bl1_init_bl2_mem_layout - -/******************************************************************************* - * Function that takes a memory layout into which BL2 has been loaded and - * populates a new memory layout for BL2 that ensures that BL1's data sections - * resident in secure RAM are not visible to BL2. + * Helper utility to calculate the BL2 memory layout taking into consideration + * the BL1 RW data assuming that it is at the top of the memory layout. ******************************************************************************/ -void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout, - meminfo_t *bl2_mem_layout) +void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout, + meminfo_t *bl2_mem_layout) { - assert(bl1_mem_layout != NULL); assert(bl2_mem_layout != NULL); @@ -71,6 +62,25 @@ void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout, flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t)); } +#if !ERROR_DEPRECATED +/******************************************************************************* + * Compatibility default implementation for deprecated API. This has a weak + * definition. Platform specific code can override it if it wishes to. + ******************************************************************************/ +#pragma weak bl1_init_bl2_mem_layout + +/******************************************************************************* + * Function that takes a memory layout into which BL2 has been loaded and + * populates a new memory layout for BL2 that ensures that BL1's data sections + * resident in secure RAM are not visible to BL2. + ******************************************************************************/ +void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout, + meminfo_t *bl2_mem_layout) +{ + bl1_calc_bl2_mem_layout(bl1_mem_layout, bl2_mem_layout); +} +#endif + /******************************************************************************* * Function to perform late architectural and platform specific initialization. * It also queries the platform to load and run next BL image. Only called @@ -157,9 +167,6 @@ void bl1_load_bl2(void) { image_desc_t *image_desc; image_info_t *image_info; - entry_point_info_t *ep_info; - meminfo_t *bl1_tzram_layout; - meminfo_t *bl2_tzram_layout; int err; /* Get the image descriptor */ @@ -168,24 +175,26 @@ void bl1_load_bl2(void) /* Get the image info */ image_info = &image_desc->image_info; - - /* Get the entry point info */ - ep_info = &image_desc->ep_info; - - /* Find out how much free trusted ram remains after BL1 load */ - bl1_tzram_layout = bl1_plat_sec_mem_layout(); - INFO("BL1: Loading BL2\n"); -#if LOAD_IMAGE_V2 - err = bl1_plat_handle_pre_image_load(); + err = bl1_plat_handle_pre_image_load(BL2_IMAGE_ID); if (err) { ERROR("Failure in pre image load handling of BL2 (%d)\n", err); plat_error_handler(err); } +#if LOAD_IMAGE_V2 err = load_auth_image(BL2_IMAGE_ID, image_info); #else + entry_point_info_t *ep_info; + meminfo_t *bl1_tzram_layout; + + /* Get the entry point info */ + ep_info = &image_desc->ep_info; + + /* Find out how much free trusted ram remains after BL1 load */ + bl1_tzram_layout = bl1_plat_sec_mem_layout(); + /* Load the BL2 image */ err = load_auth_image(bl1_tzram_layout, BL2_IMAGE_ID, @@ -200,32 +209,14 @@ void bl1_load_bl2(void) plat_error_handler(err); } -#if LOAD_IMAGE_V2 /* Allow platform to handle image information. */ - err = bl1_plat_handle_post_image_load(); + err = bl1_plat_handle_post_image_load(BL2_IMAGE_ID); if (err) { ERROR("Failure in post image load handling of BL2 (%d)\n", err); plat_error_handler(err); } - /* - * Create a new layout of memory for BL2 as seen by BL1 i.e. - * tell it the amount of total and free memory available. - * This layout is created at the first free address visible - * to BL2. BL2 will read the memory layout before using its - * memory for other purposes. - */ - bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->total_base; -#else - bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->free_base; -#endif /* LOAD_IMAGE_V2 */ - - bl1_init_bl2_mem_layout(bl1_tzram_layout, bl2_tzram_layout); - - ep_info->args.arg1 = (uintptr_t)bl2_tzram_layout; NOTICE("BL1: Booting BL2\n"); - VERBOSE("BL1: BL2 memory layout address = %p\n", - (void *) bl2_tzram_layout); } /******************************************************************************* diff --git a/bl2/aarch32/bl2_entrypoint.S b/bl2/aarch32/bl2_entrypoint.S index e6fa5b98..d215f484 100644 --- a/bl2/aarch32/bl2_entrypoint.S +++ b/bl2/aarch32/bl2_entrypoint.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -26,12 +26,14 @@ vector_base bl2_vector_table func bl2_entrypoint /*--------------------------------------------- - * Save from r1 the extents of the trusted ram - * available to BL2 for future use. - * r0 is not currently used. + * Save arguments x0 - x3 from BL1 for future + * use. * --------------------------------------------- */ - mov r11, r1 + mov r9, r0 + mov r10, r1 + mov r11, r2 + mov r12, r3 /* --------------------------------------------- * Set the exception vector to something sane. @@ -111,8 +113,11 @@ func bl2_entrypoint * specific early arch. setup e.g. mmu setup * --------------------------------------------- */ - mov r0, r11 - bl bl2_early_platform_setup + mov r0, r9 + mov r1, r10 + mov r2, r11 + mov r3, r12 + bl bl2_early_platform_setup2 bl bl2_plat_arch_setup /* --------------------------------------------- diff --git a/bl2/aarch64/bl2_entrypoint.S b/bl2/aarch64/bl2_entrypoint.S index 3ab8b5ab..bc8cbfd6 100644 --- a/bl2/aarch64/bl2_entrypoint.S +++ b/bl2/aarch64/bl2_entrypoint.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -15,12 +15,14 @@ func bl2_entrypoint /*--------------------------------------------- - * Save from x1 the extents of the tzram - * available to BL2 for future use. - * x0 is not currently used. + * Save arguments x0 - x3 from BL1 for future + * use. * --------------------------------------------- */ - mov x20, x1 + mov x20, x0 + mov x21, x1 + mov x22, x2 + mov x23, x3 /* --------------------------------------------- * Set the exception vector to something sane. @@ -103,7 +105,11 @@ func bl2_entrypoint * --------------------------------------------- */ mov x0, x20 - bl bl2_early_platform_setup + mov x1, x21 + mov x2, x22 + mov x3, x23 + bl bl2_early_platform_setup2 + bl bl2_plat_arch_setup /* --------------------------------------------- @@ -29,7 +29,6 @@ BL2_LINKERFILE := bl2/bl2.ld.S else BL2_SOURCES += bl2/${ARCH}/bl2_el3_entrypoint.S \ bl2/${ARCH}/bl2_el3_exceptions.S \ - plat/common/plat_bl2_el3_common.c \ lib/cpus/${ARCH}/cpu_helpers.S \ lib/cpus/errata_report.c BL2_LINKERFILE := bl2/bl2_el3.ld.S diff --git a/bl31/aarch64/bl31_entrypoint.S b/bl31/aarch64/bl31_entrypoint.S index 419927d8..924f295a 100644 --- a/bl31/aarch64/bl31_entrypoint.S +++ b/bl31/aarch64/bl31_entrypoint.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -23,13 +23,13 @@ func bl31_entrypoint #if !RESET_TO_BL31 /* --------------------------------------------------------------- - * Preceding bootloader has populated x0 with a pointer to a - * 'bl31_params' structure & x1 with a pointer to platform - * specific structure + * Stash the previous bootloader arguments x0 - x3 for later use. * --------------------------------------------------------------- */ mov x20, x0 mov x21, x1 + mov x22, x2 + mov x23, x3 /* --------------------------------------------------------------------- * For !RESET_TO_BL31 systems, only the primary CPU ever reaches @@ -47,13 +47,6 @@ func bl31_entrypoint _init_memory=0 \ _init_c_runtime=1 \ _exception_vectors=runtime_exceptions - - /* --------------------------------------------------------------------- - * Relay the previous bootloader's arguments to the platform layer - * --------------------------------------------------------------------- - */ - mov x0, x20 - mov x1, x21 #else /* --------------------------------------------------------------------- * For RESET_TO_BL31 systems which have a programmable reset address, @@ -75,15 +68,20 @@ func bl31_entrypoint * arguments passed to the platform layer to reflect that. * --------------------------------------------------------------------- */ - mov x0, 0 - mov x1, 0 + mov x20, 0 + mov x21, 0 + mov x22, 0 + mov x23, 0 #endif /* RESET_TO_BL31 */ - /* --------------------------------------------- * Perform platform specific early arch. setup * --------------------------------------------- */ - bl bl31_early_platform_setup + mov x0, x20 + mov x1, x21 + mov x2, x22 + mov x3, x23 + bl bl31_early_platform_setup2 bl bl31_plat_arch_setup /* --------------------------------------------- diff --git a/bl32/sp_min/aarch32/entrypoint.S b/bl32/sp_min/aarch32/entrypoint.S index e7528d38..3dd23696 100644 --- a/bl32/sp_min/aarch32/entrypoint.S +++ b/bl32/sp_min/aarch32/entrypoint.S @@ -64,8 +64,10 @@ func sp_min_entrypoint * specific structure * --------------------------------------------------------------- */ - mov r11, r0 - mov r12, r1 + mov r9, r0 + mov r10, r1 + mov r11, r2 + mov r12, r3 /* --------------------------------------------------------------------- * For !RESET_TO_SP_MIN systems, only the primary CPU ever reaches @@ -88,8 +90,6 @@ func sp_min_entrypoint * Relay the previous bootloader's arguments to the platform layer * --------------------------------------------------------------------- */ - mov r0, r11 - mov r1, r12 #else /* --------------------------------------------------------------------- * For RESET_TO_SP_MIN systems which have a programmable reset address, @@ -111,15 +111,22 @@ func sp_min_entrypoint * Zero the arguments passed to the platform layer to reflect that. * --------------------------------------------------------------------- */ - mov r0, #0 - mov r1, #0 + mov r9, #0 + mov r10, #0 + mov r11, #0 + mov r12, #0 + #endif /* RESET_TO_SP_MIN */ #if SP_MIN_WITH_SECURE_FIQ route_fiq_to_sp_min r4 #endif - bl sp_min_early_platform_setup + mov r0, r9 + mov r1, r10 + mov r2, r11 + mov r3, r12 + bl sp_min_early_platform_setup2 bl sp_min_plat_arch_setup /* Jump to the main function */ diff --git a/common/desc_image_load.c b/common/desc_image_load.c index e68e69ca..672b80b0 100644 --- a/common/desc_image_load.c +++ b/common/desc_image_load.c @@ -190,3 +190,65 @@ bl_params_t *get_next_bl_params_from_mem_params_desc(void) return &next_bl_params; } + +/******************************************************************************* + * This function populates the entry point information with the corresponding + * config file for all executable BL images described in bl_params. + ******************************************************************************/ +void populate_next_bl_params_config(bl_params_t *bl2_to_next_bl_params) +{ + bl_params_node_t *params_node; + unsigned int fw_config_id; + uintptr_t hw_config_base = 0, fw_config_base; + bl_mem_params_node_t *mem_params; + + assert(bl2_to_next_bl_params != NULL); + + /* + * Get the `bl_mem_params_node_t` corresponding to HW_CONFIG + * if available. + */ + mem_params = get_bl_mem_params_node(HW_CONFIG_ID); + if (mem_params != NULL) + hw_config_base = mem_params->image_info.image_base; + + for (params_node = bl2_to_next_bl_params->head; params_node != NULL; + params_node = params_node->next_params_info) { + + fw_config_base = 0; + + switch (params_node->image_id) { + case BL31_IMAGE_ID: + fw_config_id = SOC_FW_CONFIG_ID; + break; + case BL32_IMAGE_ID: + fw_config_id = TOS_FW_CONFIG_ID; + break; + case BL33_IMAGE_ID: + fw_config_id = NT_FW_CONFIG_ID; + break; + default: + fw_config_id = INVALID_IMAGE_ID; + break; + } + + if (fw_config_id != INVALID_IMAGE_ID) { + mem_params = get_bl_mem_params_node(fw_config_id); + if (mem_params != NULL) + fw_config_base = mem_params->image_info.image_base; + } + + /* + * Pass hw and tb_fw config addresses to next images. NOTE - for + * EL3 runtime images (BL31 for AArch64 and BL32 for AArch32), + * arg0 is already used by generic code. + */ + if (params_node == bl2_to_next_bl_params->head) { + params_node->ep_info->args.arg1 = fw_config_base; + params_node->ep_info->args.arg2 = hw_config_base; + } else { + params_node->ep_info->args.arg0 = fw_config_base; + params_node->ep_info->args.arg1 = hw_config_base; + } + } +} diff --git a/common/fdt_wrappers.c b/common/fdt_wrappers.c new file mode 100644 index 00000000..1a726a8a --- /dev/null +++ b/common/fdt_wrappers.c @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* Helper functions to offer easier navigation of Device Tree Blob */ + +#include <assert.h> +#include <debug.h> +#include <fdt_wrappers.h> +#include <libfdt.h> + +/* + * Read cells from a given property of the given node. At most 2 cells of the + * property are read, and pointer is updated. Returns 0 on success, and -1 upon + * error + */ +int fdtw_read_cells(const void *dtb, int node, const char *prop, + unsigned int cells, void *value) +{ + const uint32_t *value_ptr; + uint32_t hi = 0, lo; + int value_len; + + assert(dtb != NULL); + assert(prop != NULL); + assert(value != NULL); + assert(node >= 0); + + /* We expect either 1 or 2 cell property */ + assert(cells <= 2U); + + /* Access property and obtain its length (in bytes) */ + value_ptr = fdt_getprop_namelen(dtb, node, prop, (int)strlen(prop), + &value_len); + if (value_ptr == NULL) { + WARN("Couldn't find property %s in dtb\n", prop); + return -1; + } + + + /* Verify that property length accords with cell length */ + if (NCELLS((unsigned int)value_len) != cells) { + WARN("Property length mismatch\n"); + return -1; + } + + if (cells == 2U) { + hi = fdt32_to_cpu(*value_ptr); + value_ptr++; + } + + lo = fdt32_to_cpu(*value_ptr); + + if (cells == 2U) + *((uint64_t *) value) = ((uint64_t) hi << 32) | lo; + else + *((uint32_t *) value) = lo; + + return 0; +} + +/* + * Write cells in place to a given property of the given node. At most 2 cells + * of the property are written. Returns 0 on success, and -1 upon error. + */ +int fdtw_write_inplace_cells(void *dtb, int node, const char *prop, + unsigned int cells, void *value) +{ + int err, len; + + assert(dtb != NULL); + assert(prop != NULL); + assert(value != NULL); + assert(node >= 0); + + /* We expect either 1 or 2 cell property */ + assert(cells <= 2U); + + if (cells == 2U) + *(uint64_t *)value = cpu_to_fdt64(*(uint64_t *)value); + else + *(uint32_t *)value = cpu_to_fdt32(*(uint32_t *)value); + + len = (int)cells * 4; + + /* Set property value in place */ + err = fdt_setprop_inplace(dtb, node, prop, value, len); + if (err != 0) { + WARN("Modify property %s failed with error %d\n", prop, err); + return -1; + } + + return 0; +} diff --git a/docs/porting-guide.rst b/docs/porting-guide.rst index ec613c84..3ea95a14 100644 --- a/docs/porting-guide.rst +++ b/docs/porting-guide.rst @@ -1179,25 +1179,6 @@ its own use. This function helps fulfill requirements 4 and 5 above. -Function : bl1\_init\_bl2\_mem\_layout() [optional] -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -:: - - Argument : meminfo *, meminfo * - Return : void - -BL1 needs to tell the next stage the amount of secure RAM available -for it to use. This information is populated in a ``meminfo`` -structure. - -Depending upon where BL2 has been loaded in secure RAM (determined by -``BL2_BASE``), BL1 calculates the amount of free memory available for BL2 to use. -BL1 also ensures that its data sections resident in secure RAM are not visible -to BL2. An illustration of how this is done in ARM standard platforms is given -in the **Memory layout on ARM development platforms** section in the -`Firmware Design`_. - Function : bl1\_plat\_prepare\_exit() [optional] ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -1264,24 +1245,24 @@ Function : bl1\_plat\_handle\_pre\_image\_load() [optional] :: - Argument : void + Argument : unsigned int image_id Return : int This function can be used by the platforms to update/use image information -for BL2. This function is currently invoked in BL1 before loading BL2, -when LOAD\_IMAGE\_V2 is enabled. +corresponding to ``image_id``. This function is invoked in BL1, both in cold +boot and FWU code path, before loading the image. Function : bl1\_plat\_handle\_post\_image\_load() [optional] ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ :: - Argument : void + Argument : unsigned int image_id Return : int This function can be used by the platforms to update/use image information -for BL2. This function is currently invoked in BL1 after loading BL2, -when LOAD\_IMAGE\_V2 is enabled. +corresponding to ``image_id``. This function is invoked in BL1, both in cold +boot and FWU code path, after loading and authenticating the image. Function : bl1\_plat\_fwu\_done() [optional] ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/drivers/auth/tbbr/tbbr_cot.c b/drivers/auth/tbbr/tbbr_cot.c index 01d6fb5a..6ad00592 100644 --- a/drivers/auth/tbbr/tbbr_cot.c +++ b/drivers/auth/tbbr/tbbr_cot.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -27,6 +27,8 @@ * established, we can reuse some of the buffers on different stages */ static unsigned char tb_fw_hash_buf[HASH_DER_LEN]; +static unsigned char tb_fw_config_hash_buf[HASH_DER_LEN]; +static unsigned char hw_config_hash_buf[HASH_DER_LEN]; static unsigned char scp_fw_hash_buf[HASH_DER_LEN]; static unsigned char soc_fw_hash_buf[HASH_DER_LEN]; static unsigned char tos_fw_hash_buf[HASH_DER_LEN]; @@ -70,6 +72,10 @@ static auth_param_type_desc_t nt_fw_content_pk = AUTH_PARAM_TYPE_DESC( static auth_param_type_desc_t tb_fw_hash = AUTH_PARAM_TYPE_DESC( AUTH_PARAM_HASH, TRUSTED_BOOT_FW_HASH_OID); +static auth_param_type_desc_t tb_fw_config_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, TRUSTED_BOOT_FW_CONFIG_HASH_OID); +static auth_param_type_desc_t hw_config_hash = AUTH_PARAM_TYPE_DESC( + AUTH_PARAM_HASH, HW_CONFIG_HASH_OID); static auth_param_type_desc_t scp_fw_hash = AUTH_PARAM_TYPE_DESC( AUTH_PARAM_HASH, SCP_FW_HASH_OID); static auth_param_type_desc_t soc_fw_hash = AUTH_PARAM_TYPE_DESC( @@ -125,6 +131,20 @@ static const auth_img_desc_t cot_desc[] = { .ptr = (void *)tb_fw_hash_buf, .len = (unsigned int)HASH_DER_LEN } + }, + [1] = { + .type_desc = &tb_fw_config_hash, + .data = { + .ptr = (void *)tb_fw_config_hash_buf, + .len = (unsigned int)HASH_DER_LEN + } + }, + [2] = { + .type_desc = &hw_config_hash, + .data = { + .ptr = (void *)hw_config_hash_buf, + .len = (unsigned int)HASH_DER_LEN + } } } }, @@ -142,6 +162,36 @@ static const auth_img_desc_t cot_desc[] = { } } }, + /* HW Config */ + [HW_CONFIG_ID] = { + .img_id = HW_CONFIG_ID, + .img_type = IMG_RAW, + .parent = &cot_desc[TRUSTED_BOOT_FW_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_HASH, + .param.hash = { + .data = &raw_data, + .hash = &hw_config_hash, + } + } + } + }, + /* TB FW Config */ + [TB_FW_CONFIG_ID] = { + .img_id = TB_FW_CONFIG_ID, + .img_type = IMG_RAW, + .parent = &cot_desc[TRUSTED_BOOT_FW_CERT_ID], + .img_auth_methods = { + [0] = { + .type = AUTH_METHOD_HASH, + .param.hash = { + .data = &raw_data, + .hash = &tb_fw_config_hash, + } + } + } + }, /* * Trusted key certificate */ diff --git a/fdts/fvp-base-gicv2-psci-aarch32.dts b/fdts/fvp-base-gicv2-psci-aarch32.dts index 1560a000..87ac68d6 100644 --- a/fdts/fvp-base-gicv2-psci-aarch32.dts +++ b/fdts/fvp-base-gicv2-psci-aarch32.dts @@ -279,7 +279,7 @@ <0 0 41 &gic 0 41 4>, <0 0 42 &gic 0 42 4>; - /include/ "rtsm_ve-motherboard.dtsi" + /include/ "rtsm_ve-motherboard-aarch32.dtsi" }; panels { diff --git a/fdts/fvp-base-gicv3-psci-aarch32.dts b/fdts/fvp-base-gicv3-psci-aarch32.dts index dd884f55..b914ca0c 100644 --- a/fdts/fvp-base-gicv3-psci-aarch32.dts +++ b/fdts/fvp-base-gicv3-psci-aarch32.dts @@ -288,7 +288,7 @@ <0 0 41 &gic 0 0 0 41 4>, <0 0 42 &gic 0 0 0 42 4>; - /include/ "rtsm_ve-motherboard.dtsi" + /include/ "rtsm_ve-motherboard-aarch32.dtsi" }; panels { diff --git a/fdts/rtsm_ve-motherboard-aarch32.dtsi b/fdts/rtsm_ve-motherboard-aarch32.dtsi new file mode 100644 index 00000000..5afbc1ee --- /dev/null +++ b/fdts/rtsm_ve-motherboard-aarch32.dtsi @@ -0,0 +1,252 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + motherboard { + arm,v2m-memory-map = "rs1"; + compatible = "arm,vexpress,v2m-p1", "simple-bus"; + #address-cells = <2>; /* SMB chipselect number and offset */ + #size-cells = <1>; + #interrupt-cells = <1>; + ranges; + + flash@0,00000000 { + compatible = "arm,vexpress-flash", "cfi-flash"; + reg = <0 0x00000000 0x04000000>, + <4 0x00000000 0x04000000>; + bank-width = <4>; + }; + + vram@2,00000000 { + compatible = "arm,vexpress-vram"; + reg = <2 0x00000000 0x00800000>; + }; + + ethernet@2,02000000 { + compatible = "smsc,lan91c111"; + reg = <2 0x02000000 0x10000>; + interrupts = <15>; + }; + + v2m_clk24mhz: clk24mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "v2m:clk24mhz"; + }; + + v2m_refclk1mhz: refclk1mhz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1000000>; + clock-output-names = "v2m:refclk1mhz"; + }; + + v2m_refclk32khz: refclk32khz { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "v2m:refclk32khz"; + }; + + iofpga@3,00000000 { + compatible = "arm,amba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 3 0 0x200000>; + + v2m_sysreg: sysreg@010000 { + compatible = "arm,vexpress-sysreg"; + reg = <0x010000 0x1000>; + gpio-controller; + #gpio-cells = <2>; + }; + + v2m_sysctl: sysctl@020000 { + compatible = "arm,sp810", "arm,primecell"; + reg = <0x020000 0x1000>; + clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>; + clock-names = "refclk", "timclk", "apb_pclk"; + #clock-cells = <1>; + clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3"; + }; + + aaci@040000 { + compatible = "arm,pl041", "arm,primecell"; + reg = <0x040000 0x1000>; + interrupts = <11>; + clocks = <&v2m_clk24mhz>; + clock-names = "apb_pclk"; + }; + + mmci@050000 { + compatible = "arm,pl180", "arm,primecell"; + reg = <0x050000 0x1000>; + interrupts = <9 10>; + cd-gpios = <&v2m_sysreg 0 0>; + wp-gpios = <&v2m_sysreg 1 0>; + max-frequency = <12000000>; + vmmc-supply = <&v2m_fixed_3v3>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "mclk", "apb_pclk"; + }; + + kmi@060000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x060000 0x1000>; + interrupts = <12>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + kmi@070000 { + compatible = "arm,pl050", "arm,primecell"; + reg = <0x070000 0x1000>; + interrupts = <13>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "KMIREFCLK", "apb_pclk"; + }; + + v2m_serial0: uart@090000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x090000 0x1000>; + interrupts = <5>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial1: uart@0a0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0a0000 0x1000>; + interrupts = <6>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial2: uart@0b0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0b0000 0x1000>; + interrupts = <7>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + v2m_serial3: uart@0c0000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x0c0000 0x1000>; + interrupts = <8>; + clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>; + clock-names = "uartclk", "apb_pclk"; + }; + + wdt@0f0000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0f0000 0x1000>; + interrupts = <0>; + clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>; + clock-names = "wdogclk", "apb_pclk"; + }; + + v2m_timer01: timer@110000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x110000 0x1000>; + interrupts = <2>; + clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + v2m_timer23: timer@120000 { + compatible = "arm,sp804", "arm,primecell"; + reg = <0x120000 0x1000>; + interrupts = <3>; + clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>; + clock-names = "timclken1", "timclken2", "apb_pclk"; + }; + + rtc@170000 { + compatible = "arm,pl031", "arm,primecell"; + reg = <0x170000 0x1000>; + interrupts = <4>; + clocks = <&v2m_clk24mhz>; + clock-names = "apb_pclk"; + }; + + clcd@1f0000 { + compatible = "arm,pl111", "arm,primecell"; + reg = <0x1f0000 0x1000>; + interrupts = <14>; + clocks = <&v2m_oscclk1>, <&v2m_clk24mhz>; + clock-names = "clcdclk", "apb_pclk"; + mode = "XVGA"; + use_dma = <0>; + framebuffer = <0x18000000 0x00180000>; + }; + + virtio_block@0130000 { + compatible = "virtio,mmio"; + reg = <0x130000 0x1000>; + interrupts = <0x2a>; + }; + }; + + v2m_fixed_3v3: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + mcc { + compatible = "arm,vexpress,config-bus", "simple-bus"; + arm,vexpress,config-bridge = <&v2m_sysreg>; + + v2m_oscclk1: osc@1 { + /* CLCD clock */ + compatible = "arm,vexpress-osc"; + arm,vexpress-sysreg,func = <1 1>; + freq-range = <23750000 63500000>; + #clock-cells = <0>; + clock-output-names = "v2m:oscclk1"; + }; + + /* + * Not supported in FVP models + * + * reset@0 { + * compatible = "arm,vexpress-reset"; + * arm,vexpress-sysreg,func = <5 0>; + * }; + */ + + muxfpga@0 { + compatible = "arm,vexpress-muxfpga"; + arm,vexpress-sysreg,func = <7 0>; + }; + + /* + * Not used - Superseded by PSCI sys_poweroff + * + * shutdown@0 { + * compatible = "arm,vexpress-shutdown"; + * arm,vexpress-sysreg,func = <8 0>; + * }; + */ + + /* + * Not used - Superseded by PSCI sys_reset + * + * reboot@0 { + * compatible = "arm,vexpress-reboot"; + * arm,vexpress-sysreg,func = <9 0>; + * }; + */ + + dvimode@0 { + compatible = "arm,vexpress-dvimode"; + arm,vexpress-sysreg,func = <11 0>; + }; + }; + }; diff --git a/include/bl1/bl1.h b/include/bl1/bl1.h index 15445235..b0421007 100644 --- a/include/bl1/bl1.h +++ b/include/bl1/bl1.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -71,5 +71,9 @@ CASSERT(FWU_NUM_SMC_CALLS == \ (FWU_SMC_FID_END - FWU_SMC_FID_START + 1),\ assert_FWU_NUM_SMC_CALLS_mismatch); +/* Utility functions */ +void bl1_calc_bl2_mem_layout(const meminfo_t *bl1_mem_layout, + meminfo_t *bl2_mem_layout); + #endif /* __ASSEMBLY__ */ #endif /* __BL1_FWU_H__ */ diff --git a/include/bl32/sp_min/platform_sp_min.h b/include/bl32/sp_min/platform_sp_min.h index 6c7e0cc0..8f6a82d9 100644 --- a/include/bl32/sp_min/platform_sp_min.h +++ b/include/bl32/sp_min/platform_sp_min.h @@ -10,8 +10,12 @@ /******************************************************************************* * Mandatory SP_MIN functions ******************************************************************************/ +#if !ERROR_DEPRECATED void sp_min_early_platform_setup(void *from_bl2, void *plat_params_from_bl2); +#endif +void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3); void sp_min_platform_setup(void); void sp_min_plat_runtime_setup(void); void sp_min_plat_arch_setup(void); diff --git a/include/common/bl_common.h b/include/common/bl_common.h index 8915ba06..6a249f5b 100644 --- a/include/common/bl_common.h +++ b/include/common/bl_common.h @@ -9,6 +9,7 @@ #include <ep_info.h> #include <param_header.h> +#include <utils_def.h> #define UP 1 #define DOWN 0 @@ -31,10 +32,10 @@ #define IMAGE_STATE_EXECUTED 4 #define IMAGE_STATE_INTERRUPTED 5 -#define IMAGE_ATTRIB_SKIP_LOADING 0x02 -#define IMAGE_ATTRIB_PLAT_SETUP 0x04 +#define IMAGE_ATTRIB_SKIP_LOADING U(0x02) +#define IMAGE_ATTRIB_PLAT_SETUP U(0x04) -#define INVALID_IMAGE_ID (0xFFFFFFFF) +#define INVALID_IMAGE_ID U(0xFFFFFFFF) /******************************************************************************* * Constants to indicate type of exception to the common exception handler. diff --git a/include/common/desc_image_load.h b/include/common/desc_image_load.h index 79f2bd7b..f183db50 100644 --- a/include/common/desc_image_load.h +++ b/include/common/desc_image_load.h @@ -33,7 +33,7 @@ int get_bl_params_node_index(unsigned int image_id); bl_mem_params_node_t *get_bl_mem_params_node(unsigned int image_id); bl_load_info_t *get_bl_load_info_from_mem_params_desc(void); bl_params_t *get_next_bl_params_from_mem_params_desc(void); - +void populate_next_bl_params_config(bl_params_t *bl2_to_next_bl_params); #endif /* LOAD_IMAGE_V2 */ #endif /* __DESC_IMAGE_LOAD_H__ */ diff --git a/include/common/fdt_wrappers.h b/include/common/fdt_wrappers.h new file mode 100644 index 00000000..18a6d103 --- /dev/null +++ b/include/common/fdt_wrappers.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/* Helper functions to offer easier navigation of Device Tree Blob */ + +#ifndef __FDT_WRAPPERS__ +#define __FDT_WRAPPERS__ + +/* Number of cells, given total length in bytes. Each cell is 4 bytes long */ +#define NCELLS(len) ((len) / 4) + +int fdtw_read_cells(const void *dtb, int node, const char *prop, + unsigned int cells, void *value); +int fdtw_write_inplace_cells(void *dtb, int node, const char *prop, + unsigned int cells, void *value); +#endif /* __FDT_WRAPPERS__ */ diff --git a/include/common/tbbr/tbbr_img_def.h b/include/common/tbbr/tbbr_img_def.h index 3e68b648..060198bc 100644 --- a/include/common/tbbr/tbbr_img_def.h +++ b/include/common/tbbr/tbbr_img_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -60,4 +60,19 @@ /* Secure Payload BL32_EXTRA2 (Trusted OS Extra2) */ #define BL32_EXTRA2_IMAGE_ID 22 +/* HW_CONFIG (e.g. Kernel DT) */ +#define HW_CONFIG_ID 23 + +/* TB_FW_CONFIG */ +#define TB_FW_CONFIG_ID 24 + +/* SOC_FW_CONFIG */ +#define SOC_FW_CONFIG_ID 25 + +/* TOS_FW_CONFIG */ +#define TOS_FW_CONFIG_ID 26 + +/* NT_FW_CONFIG */ +#define NT_FW_CONFIG_ID 27 + #endif /* __TBBR_IMG_DEF_H__ */ diff --git a/include/lib/cpus/aarch64/cortex_a75.h b/include/lib/cpus/aarch64/cortex_a75.h index 940125da..20f02518 100644 --- a/include/lib/cpus/aarch64/cortex_a75.h +++ b/include/lib/cpus/aarch64/cortex_a75.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,28 +19,6 @@ /* Definitions of register field mask in CORTEX_A75_CPUPWRCTLR_EL1 */ #define CORTEX_A75_CORE_PWRDN_EN_MASK 0x1 -/******************************************************************************* - * CPU Activity Monitor Unit register specific definitions. - ******************************************************************************/ -#define CPUAMCNTENCLR_EL0 S3_3_C15_C9_7 -#define CPUAMCNTENSET_EL0 S3_3_C15_C9_6 -#define CPUAMCFGR_EL0 S3_3_C15_C10_6 -#define CPUAMUSERENR_EL0 S3_3_C15_C10_7 - -/* Activity Monitor Event Counter Registers */ -#define CPUAMEVCNTR0_EL0 S3_3_C15_C9_0 -#define CPUAMEVCNTR1_EL0 S3_3_C15_C9_1 -#define CPUAMEVCNTR2_EL0 S3_3_C15_C9_2 -#define CPUAMEVCNTR3_EL0 S3_3_C15_C9_3 -#define CPUAMEVCNTR4_EL0 S3_3_C15_C9_4 - -/* Activity Monitor Event Type Registers */ -#define CPUAMEVTYPER0_EL0 S3_3_C15_C10_0 -#define CPUAMEVTYPER1_EL0 S3_3_C15_C10_1 -#define CPUAMEVTYPER2_EL0 S3_3_C15_C10_2 -#define CPUAMEVTYPER3_EL0 S3_3_C15_C10_3 -#define CPUAMEVTYPER4_EL0 S3_3_C15_C10_4 - #define CORTEX_A75_ACTLR_AMEN_BIT (U(1) << 4) /* @@ -50,9 +28,9 @@ * CPUAMEVTYPER<n> register and are disabled by default. Platforms may * enable this with suitable programming. */ -#define CORTEX_A75_AMU_NR_COUNTERS 5 -#define CORTEX_A75_AMU_GROUP0_MASK 0x7 -#define CORTEX_A75_AMU_GROUP1_MASK (0 << 3) +#define CORTEX_A75_AMU_NR_COUNTERS U(5) +#define CORTEX_A75_AMU_GROUP0_MASK U(0x7) +#define CORTEX_A75_AMU_GROUP1_MASK (U(0) << 3) #ifndef __ASSEMBLY__ #include <stdint.h> diff --git a/include/lib/cpus/aarch64/cpuamu.h b/include/lib/cpus/aarch64/cpuamu.h new file mode 100644 index 00000000..960a5248 --- /dev/null +++ b/include/lib/cpus/aarch64/cpuamu.h @@ -0,0 +1,48 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef __CPUAMU_H__ +#define __CPUAMU_H__ + +/******************************************************************************* + * CPU Activity Monitor Unit register specific definitions. + ******************************************************************************/ +#define CPUAMCNTENCLR_EL0 S3_3_C15_C9_7 +#define CPUAMCNTENSET_EL0 S3_3_C15_C9_6 +#define CPUAMCFGR_EL0 S3_3_C15_C10_6 +#define CPUAMUSERENR_EL0 S3_3_C15_C10_7 + +/* Activity Monitor Event Counter Registers */ +#define CPUAMEVCNTR0_EL0 S3_3_C15_C9_0 +#define CPUAMEVCNTR1_EL0 S3_3_C15_C9_1 +#define CPUAMEVCNTR2_EL0 S3_3_C15_C9_2 +#define CPUAMEVCNTR3_EL0 S3_3_C15_C9_3 +#define CPUAMEVCNTR4_EL0 S3_3_C15_C9_4 + +/* Activity Monitor Event Type Registers */ +#define CPUAMEVTYPER0_EL0 S3_3_C15_C10_0 +#define CPUAMEVTYPER1_EL0 S3_3_C15_C10_1 +#define CPUAMEVTYPER2_EL0 S3_3_C15_C10_2 +#define CPUAMEVTYPER3_EL0 S3_3_C15_C10_3 +#define CPUAMEVTYPER4_EL0 S3_3_C15_C10_4 + +#ifndef __ASSEMBLY__ +#include <stdint.h> + +uint64_t cpuamu_cnt_read(int idx); +void cpuamu_cnt_write(int idx, uint64_t val); +unsigned int cpuamu_read_cpuamcntenset_el0(void); +unsigned int cpuamu_read_cpuamcntenclr_el0(void); +void cpuamu_write_cpuamcntenset_el0(unsigned int mask); +void cpuamu_write_cpuamcntenclr_el0(unsigned int mask); + +int midr_match(unsigned int cpu_midr); +void cpuamu_context_save(unsigned int nr_counters); +void cpuamu_context_restore(unsigned int nr_counters); + +#endif /* __ASSEMBLY__ */ + +#endif /* __CPUAMU_H__ */ diff --git a/include/lib/extensions/spe.h b/include/lib/extensions/spe.h index 8a74127a..b2b188ef 100644 --- a/include/lib/extensions/spe.h +++ b/include/lib/extensions/spe.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,7 @@ #ifndef __SPE_H__ #define __SPE_H__ +int spe_supported(void); void spe_enable(int el2_unused); void spe_disable(void); diff --git a/include/lib/extensions/sve.h b/include/lib/extensions/sve.h index 28923e3f..9c7f37f2 100644 --- a/include/lib/extensions/sve.h +++ b/include/lib/extensions/sve.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,7 @@ #ifndef __SVE_H__ #define __SVE_H__ +int sve_supported(void); void sve_enable(int el2_unused); #endif /* __SVE_H__ */ diff --git a/include/plat/arm/board/common/board_arm_def.h b/include/plat/arm/board/common/board_arm_def.h index 888629e3..12a21fb7 100644 --- a/include/plat/arm/board/common/board_arm_def.h +++ b/include/plat/arm/board/common/board_arm_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h index 697a0b04..9e6c7d27 100644 --- a/include/plat/arm/common/arm_def.h +++ b/include/plat/arm/common/arm_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -306,6 +306,12 @@ */ #define CACHE_WRITEBACK_GRANULE (1 << ARM_CACHE_WRITEBACK_SHIFT) +/* + * To enable TB_FW_CONFIG to be loaded by BL1, define the corresponding base + * and limit. Leave enough space of BL2 meminfo. + */ +#define ARM_TB_FW_CONFIG_BASE ARM_BL_RAM_BASE + sizeof(meminfo_t) +#define ARM_TB_FW_CONFIG_LIMIT BL2_LIMIT /******************************************************************************* * BL1 specific defines. diff --git a/include/plat/arm/common/arm_dyn_cfg_helpers.h b/include/plat/arm/common/arm_dyn_cfg_helpers.h new file mode 100644 index 00000000..4a0f6397 --- /dev/null +++ b/include/plat/arm/common/arm_dyn_cfg_helpers.h @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +#ifndef __ARM_DYN_CFG_HELPERS_H__ +#define __ARM_DYN_CFG_HELPERS_H__ + +#include <stdint.h> + +/* Function declaration */ +int arm_dyn_get_hwconfig_info(void *dtb, int node, + uint64_t *hw_config_addr, uint32_t *hw_config_size); +int arm_dyn_tb_fw_cfg_init(void *dtb, int *node); + +#endif /* __ARM_DYN_CFG_HELPERS_H__ */ diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h index dfd7a204..b2c7bd27 100644 --- a/include/plat/arm/common/plat_arm.h +++ b/include/plat/arm/common/plat_arm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -19,6 +19,7 @@ struct bl31_params; struct meminfo; struct image_info; +struct bl_params; #define ARM_CASSERT_MMAP \ CASSERT((ARRAY_SIZE(plat_arm_mmap) + ARM_BL_REGIONS) \ @@ -138,7 +139,7 @@ void arm_bl1_platform_setup(void); void arm_bl1_plat_arch_setup(void); /* BL2 utility functions */ -void arm_bl2_early_platform_setup(struct meminfo *mem_layout); +void arm_bl2_early_platform_setup(uintptr_t tb_fw_config, struct meminfo *mem_layout); void arm_bl2_platform_setup(void); void arm_bl2_plat_arch_setup(void); uint32_t arm_get_spsr_for_bl32_entry(void); @@ -157,11 +158,11 @@ void arm_bl2u_plat_arch_setup(void); /* BL31 utility functions */ #if LOAD_IMAGE_V2 -void arm_bl31_early_platform_setup(void *from_bl2, - void *plat_params_from_bl2); +void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, + uintptr_t hw_config, void *plat_params_from_bl2); #else -void arm_bl31_early_platform_setup(struct bl31_params *from_bl2, - void *plat_params_from_bl2); +void arm_bl31_early_platform_setup(struct bl31_params *from_bl2, uintptr_t soc_fw_config, + uintptr_t hw_config, void *plat_params_from_bl2); #endif /* LOAD_IMAGE_V2 */ void arm_bl31_platform_setup(void); void arm_bl31_plat_runtime_setup(void); @@ -171,13 +172,18 @@ void arm_bl31_plat_arch_setup(void); void arm_tsp_early_platform_setup(void); /* SP_MIN utility functions */ -void arm_sp_min_early_platform_setup(void *from_bl2, - void *plat_params_from_bl2); +void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config, + uintptr_t hw_config, void *plat_params_from_bl2); void arm_sp_min_plat_runtime_setup(void); /* FIP TOC validity check */ int arm_io_is_toc_valid(void); +/* Utility functions for Dynamic Config */ +void arm_load_tb_fw_config(void); +void arm_bl2_set_tb_cfg_addr(void *dtb); +void arm_bl2_dyn_cfg_init(void); + /* * Mandatory functions required in ARM standard platforms */ diff --git a/include/plat/common/platform.h b/include/plat/common/platform.h index e2f1cfdc..411202da 100644 --- a/include/plat/common/platform.h +++ b/include/plat/common/platform.h @@ -134,9 +134,10 @@ int bl1_plat_mem_check(uintptr_t mem_base, unsigned int mem_size, /******************************************************************************* * Optional BL1 functions (may be overridden) ******************************************************************************/ +#if !ERROR_DEPRECATED void bl1_init_bl2_mem_layout(const struct meminfo *bl1_mem_layout, struct meminfo *bl2_mem_layout); - +#endif /* * The following functions are used for image loading process in BL1. */ @@ -155,20 +156,20 @@ struct image_desc *bl1_plat_get_image_desc(unsigned int image_id); */ __dead2 void bl1_plat_fwu_done(void *client_cookie, void *reserved); -#if LOAD_IMAGE_V2 /* - * This function can be used by the platforms to update/use image - * information for BL2. + * This BL1 function can be used by the platforms to update/use image + * information for a given `image_id`. */ -int bl1_plat_handle_pre_image_load(void); -int bl1_plat_handle_post_image_load(void); - -#endif /* LOAD_IMAGE_V2 */ +int bl1_plat_handle_pre_image_load(unsigned int image_id); +int bl1_plat_handle_post_image_load(unsigned int image_id); /******************************************************************************* * Mandatory BL2 functions ******************************************************************************/ +void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3); +#if !ERROR_DEPRECATED void bl2_early_platform_setup(struct meminfo *mem_layout); +#endif void bl2_plat_arch_setup(void); void bl2_platform_setup(void); struct meminfo *bl2_plat_sec_mem_layout(void); @@ -280,6 +281,7 @@ int bl2u_plat_handle_scp_bl2u(void); /******************************************************************************* * Mandatory BL31 functions ******************************************************************************/ +#if !ERROR_DEPRECATED #if LOAD_IMAGE_V2 void bl31_early_platform_setup(void *from_bl2, void *plat_params_from_bl2); @@ -287,6 +289,9 @@ void bl31_early_platform_setup(void *from_bl2, void bl31_early_platform_setup(struct bl31_params *from_bl2, void *plat_params_from_bl2); #endif +#endif /* ERROR_DEPRECATED */ +void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3); void bl31_plat_arch_setup(void); void bl31_platform_setup(void); void bl31_plat_runtime_setup(void); diff --git a/include/tools_share/firmware_image_package.h b/include/tools_share/firmware_image_package.h index c39e6f02..b7fac07f 100644 --- a/include/tools_share/firmware_image_package.h +++ b/include/tools_share/firmware_image_package.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -63,6 +63,11 @@ {0x11449fa4, 0x635e, 0x11e4, 0x87, 0x28, {0x3f, 0x05, 0x72, 0x2a, 0xf3, 0x3d} } #define UUID_NON_TRUSTED_FW_CONTENT_CERT \ {0xf3c1c48e, 0x635d, 0x11e4, 0xa7, 0xa9, {0x87, 0xee, 0x40, 0xb2, 0x3f, 0xa7} } +/* Dynamic configs */ +#define UUID_HW_CONFIG \ + {0xd9f1b808, 0xcfc9, 0x4993, 0xa9, 0x62, {0x6f, 0xbc, 0x6b, 0x72, 0x65, 0xcc} } +#define UUID_TB_FW_CONFIG \ + {0xff58046c, 0x6baf, 0x4f7d, 0x82, 0xed, {0xaa, 0x27, 0xbc, 0x69, 0xbf, 0xd2} } typedef struct fip_toc_header { uint32_t name; diff --git a/include/tools_share/tbbr_oid.h b/include/tools_share/tbbr_oid.h index e57790c6..18ddbdc2 100644 --- a/include/tools_share/tbbr_oid.h +++ b/include/tools_share/tbbr_oid.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -41,7 +41,8 @@ /* TrustedBootFirmwareHash - BL2 */ #define TRUSTED_BOOT_FW_HASH_OID "1.3.6.1.4.1.4128.2100.201" - +#define TRUSTED_BOOT_FW_CONFIG_HASH_OID "1.3.6.1.4.1.4128.2100.202" +#define HW_CONFIG_HASH_OID "1.3.6.1.4.1.4128.2100.203" /* * Trusted Key Certificate diff --git a/lib/cpus/aarch64/cortex_a75.S b/lib/cpus/aarch64/cortex_a75.S index 946f9884..12ea304d 100644 --- a/lib/cpus/aarch64/cortex_a75.S +++ b/lib/cpus/aarch64/cortex_a75.S @@ -6,108 +6,9 @@ #include <arch.h> #include <asm_macros.S> -#include <bl_common.h> -#include <cpu_macros.S> -#include <plat_macros.S> #include <cortex_a75.h> - - .globl cortex_a75_amu_cnt_read - .globl cortex_a75_amu_cnt_write - .globl cortex_a75_amu_read_cpuamcntenset_el0 - .globl cortex_a75_amu_read_cpuamcntenclr_el0 - .globl cortex_a75_amu_write_cpuamcntenset_el0 - .globl cortex_a75_amu_write_cpuamcntenclr_el0 - -/* - * uint64_t cortex_a75_amu_cnt_read(int idx); - * - * Given `idx`, read the corresponding AMU counter - * and return it in `x0`. - */ -func cortex_a75_amu_cnt_read - adr x1, 1f - lsl x0, x0, #3 - add x1, x1, x0 - br x1 - -1: - mrs x0, CPUAMEVCNTR0_EL0 - ret - mrs x0, CPUAMEVCNTR1_EL0 - ret - mrs x0, CPUAMEVCNTR2_EL0 - ret - mrs x0, CPUAMEVCNTR3_EL0 - ret - mrs x0, CPUAMEVCNTR4_EL0 - ret -endfunc cortex_a75_amu_cnt_read - -/* - * void cortex_a75_amu_cnt_write(int idx, uint64_t val); - * - * Given `idx`, write `val` to the corresponding AMU counter. - */ -func cortex_a75_amu_cnt_write - adr x2, 1f - lsl x0, x0, #3 - add x2, x2, x0 - br x2 - -1: - msr CPUAMEVCNTR0_EL0, x0 - ret - msr CPUAMEVCNTR1_EL0, x0 - ret - msr CPUAMEVCNTR2_EL0, x0 - ret - msr CPUAMEVCNTR3_EL0, x0 - ret - msr CPUAMEVCNTR4_EL0, x0 - ret -endfunc cortex_a75_amu_cnt_write - -/* - * unsigned int cortex_a75_amu_read_cpuamcntenset_el0(void); - * - * Read the `CPUAMCNTENSET_EL0` CPU register and return - * it in `x0`. - */ -func cortex_a75_amu_read_cpuamcntenset_el0 - mrs x0, CPUAMCNTENSET_EL0 - ret -endfunc cortex_a75_amu_read_cpuamcntenset_el0 - -/* - * unsigned int cortex_a75_amu_read_cpuamcntenclr_el0(void); - * - * Read the `CPUAMCNTENCLR_EL0` CPU register and return - * it in `x0`. - */ -func cortex_a75_amu_read_cpuamcntenclr_el0 - mrs x0, CPUAMCNTENCLR_EL0 - ret -endfunc cortex_a75_amu_read_cpuamcntenclr_el0 - -/* - * void cortex_a75_amu_write_cpuamcntenset_el0(unsigned int mask); - * - * Write `mask` to the `CPUAMCNTENSET_EL0` CPU register. - */ -func cortex_a75_amu_write_cpuamcntenset_el0 - msr CPUAMCNTENSET_EL0, x0 - ret -endfunc cortex_a75_amu_write_cpuamcntenset_el0 - -/* - * void cortex_a75_amu_write_cpuamcntenclr_el0(unsigned int mask); - * - * Write `mask` to the `CPUAMCNTENCLR_EL0` CPU register. - */ -func cortex_a75_amu_write_cpuamcntenclr_el0 - mrs x0, CPUAMCNTENCLR_EL0 - ret -endfunc cortex_a75_amu_write_cpuamcntenclr_el0 +#include <cpuamu.h> +#include <cpu_macros.S> func cortex_a75_reset_func #if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 diff --git a/lib/cpus/aarch64/cortex_a75_pubsub.c b/lib/cpus/aarch64/cortex_a75_pubsub.c index a1ffcb04..16f62f47 100644 --- a/lib/cpus/aarch64/cortex_a75_pubsub.c +++ b/lib/cpus/aarch64/cortex_a75_pubsub.c @@ -1,73 +1,24 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <cortex_a75.h> -#include <platform.h> +#include <cpuamu.h> #include <pubsub_events.h> -struct amu_ctx { - uint64_t cnts[CORTEX_A75_AMU_NR_COUNTERS]; - uint16_t mask; -}; - -static struct amu_ctx amu_ctxs[PLATFORM_CORE_COUNT]; - static void *cortex_a75_context_save(const void *arg) { - struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()]; - unsigned int midr; - unsigned int midr_mask; - int i; - - midr = read_midr(); - midr_mask = (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | - (MIDR_PN_MASK << MIDR_PN_SHIFT); - if ((midr & midr_mask) != (CORTEX_A75_MIDR & midr_mask)) - return 0; - - /* Save counter configuration */ - ctx->mask = cortex_a75_amu_read_cpuamcntenset_el0(); - - /* Ensure counters are disabled */ - cortex_a75_amu_write_cpuamcntenclr_el0(ctx->mask); - isb(); - - /* Save counters */ - for (i = 0; i < CORTEX_A75_AMU_NR_COUNTERS; i++) - ctx->cnts[i] = cortex_a75_amu_cnt_read(i); - + if (midr_match(CORTEX_A75_MIDR) != 0) + cpuamu_context_save(CORTEX_A75_AMU_NR_COUNTERS); return 0; } static void *cortex_a75_context_restore(const void *arg) { - struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()]; - unsigned int midr; - unsigned int midr_mask; - int i; - - midr = read_midr(); - midr_mask = (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | - (MIDR_PN_MASK << MIDR_PN_SHIFT); - if ((midr & midr_mask) != (CORTEX_A75_MIDR & midr_mask)) - return 0; - - ctx = &amu_ctxs[plat_my_core_pos()]; - - /* Counters were disabled in `cortex_a75_context_save()` */ - assert(cortex_a75_amu_read_cpuamcntenset_el0() == 0); - - /* Restore counters */ - for (i = 0; i < CORTEX_A75_AMU_NR_COUNTERS; i++) - cortex_a75_amu_cnt_write(i, ctx->cnts[i]); - isb(); - - /* Restore counter configuration */ - cortex_a75_amu_write_cpuamcntenset_el0(ctx->mask); - + if (midr_match(CORTEX_A75_MIDR) != 0) + cpuamu_context_restore(CORTEX_A75_AMU_NR_COUNTERS); return 0; } diff --git a/lib/cpus/aarch64/cpuamu.c b/lib/cpus/aarch64/cpuamu.c new file mode 100644 index 00000000..b9bad860 --- /dev/null +++ b/lib/cpus/aarch64/cpuamu.c @@ -0,0 +1,70 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <cpuamu.h> +#include <platform.h> +#include <pubsub_events.h> + +#define CPUAMU_NR_COUNTERS 5U + +struct amu_ctx { + uint64_t cnts[CPUAMU_NR_COUNTERS]; + unsigned int mask; +}; + +static struct amu_ctx amu_ctxs[PLATFORM_CORE_COUNT]; + +int midr_match(unsigned int cpu_midr) +{ + unsigned int midr, midr_mask; + + midr = (unsigned int)read_midr(); + midr_mask = (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | + (MIDR_PN_MASK << MIDR_PN_SHIFT); + return ((midr & midr_mask) == (cpu_midr & midr_mask)); +} + +void cpuamu_context_save(unsigned int nr_counters) +{ + struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()]; + unsigned int i; + + assert(nr_counters <= CPUAMU_NR_COUNTERS); + + /* Save counter configuration */ + ctx->mask = cpuamu_read_cpuamcntenset_el0(); + + /* Disable counters */ + cpuamu_write_cpuamcntenclr_el0(ctx->mask); + isb(); + + /* Save counters */ + for (i = 0; i < nr_counters; i++) + ctx->cnts[i] = cpuamu_cnt_read(i); +} + +void cpuamu_context_restore(unsigned int nr_counters) +{ + struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()]; + unsigned int i; + + assert(nr_counters <= CPUAMU_NR_COUNTERS); + + /* + * Disable counters. They were enabled early in the + * CPU reset function. + */ + cpuamu_write_cpuamcntenclr_el0(ctx->mask); + isb(); + + /* Restore counters */ + for (i = 0; i < nr_counters; i++) + cpuamu_cnt_write(i, ctx->cnts[i]); + isb(); + + /* Restore counter configuration */ + cpuamu_write_cpuamcntenset_el0(ctx->mask); +} diff --git a/lib/cpus/aarch64/cpuamu_helpers.S b/lib/cpus/aarch64/cpuamu_helpers.S new file mode 100644 index 00000000..8965d6d0 --- /dev/null +++ b/lib/cpus/aarch64/cpuamu_helpers.S @@ -0,0 +1,107 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch.h> +#include <asm_macros.S> +#include <cpuamu.h> + + .globl cpuamu_cnt_read + .globl cpuamu_cnt_write + .globl cpuamu_read_cpuamcntenset_el0 + .globl cpuamu_read_cpuamcntenclr_el0 + .globl cpuamu_write_cpuamcntenset_el0 + .globl cpuamu_write_cpuamcntenclr_el0 + +/* + * uint64_t cpuamu_cnt_read(int idx); + * + * Given `idx`, read the corresponding AMU counter + * and return it in `x0`. + */ +func cpuamu_cnt_read + adr x1, 1f + lsl x0, x0, #3 + add x1, x1, x0 + br x1 + +1: + mrs x0, CPUAMEVCNTR0_EL0 + ret + mrs x0, CPUAMEVCNTR1_EL0 + ret + mrs x0, CPUAMEVCNTR2_EL0 + ret + mrs x0, CPUAMEVCNTR3_EL0 + ret + mrs x0, CPUAMEVCNTR4_EL0 + ret +endfunc cpuamu_cnt_read + +/* + * void cpuamu_cnt_write(int idx, uint64_t val); + * + * Given `idx`, write `val` to the corresponding AMU counter. + */ +func cpuamu_cnt_write + adr x2, 1f + lsl x0, x0, #3 + add x2, x2, x0 + br x2 + +1: + msr CPUAMEVCNTR0_EL0, x0 + ret + msr CPUAMEVCNTR1_EL0, x0 + ret + msr CPUAMEVCNTR2_EL0, x0 + ret + msr CPUAMEVCNTR3_EL0, x0 + ret + msr CPUAMEVCNTR4_EL0, x0 + ret +endfunc cpuamu_cnt_write + +/* + * unsigned int cpuamu_read_cpuamcntenset_el0(void); + * + * Read the `CPUAMCNTENSET_EL0` CPU register and return + * it in `x0`. + */ +func cpuamu_read_cpuamcntenset_el0 + mrs x0, CPUAMCNTENSET_EL0 + ret +endfunc cpuamu_read_cpuamcntenset_el0 + +/* + * unsigned int cpuamu_read_cpuamcntenclr_el0(void); + * + * Read the `CPUAMCNTENCLR_EL0` CPU register and return + * it in `x0`. + */ +func cpuamu_read_cpuamcntenclr_el0 + mrs x0, CPUAMCNTENCLR_EL0 + ret +endfunc cpuamu_read_cpuamcntenclr_el0 + +/* + * void cpuamu_write_cpuamcntenset_el0(unsigned int mask); + * + * Write `mask` to the `CPUAMCNTENSET_EL0` CPU register. + */ +func cpuamu_write_cpuamcntenset_el0 + msr CPUAMCNTENSET_EL0, x0 + ret +endfunc cpuamu_write_cpuamcntenset_el0 + +/* + * void cpuamu_write_cpuamcntenclr_el0(unsigned int mask); + * + * Write `mask` to the `CPUAMCNTENCLR_EL0` CPU register. + */ +func cpuamu_write_cpuamcntenclr_el0 + msr CPUAMCNTENCLR_EL0, x0 + ret +endfunc cpuamu_write_cpuamcntenclr_el0 diff --git a/lib/extensions/amu/aarch32/amu.c b/lib/extensions/amu/aarch32/amu.c index 68cc4b34..05c98f1c 100644 --- a/lib/extensions/amu/aarch32/amu.c +++ b/lib/extensions/amu/aarch32/amu.c @@ -30,7 +30,7 @@ int amu_supported(void) void amu_enable(int el2_unused) { - if (!amu_supported()) + if (amu_supported() == 0) return; if (el2_unused) { @@ -54,7 +54,7 @@ void amu_enable(int el2_unused) /* Read the group 0 counter identified by the given `idx`. */ uint64_t amu_group0_cnt_read(int idx) { - assert(amu_supported()); + assert(amu_supported() != 0); assert(idx >= 0 && idx < AMU_GROUP0_NR_COUNTERS); return amu_group0_cnt_read_internal(idx); @@ -63,7 +63,7 @@ uint64_t amu_group0_cnt_read(int idx) /* Write the group 0 counter identified by the given `idx` with `val`. */ void amu_group0_cnt_write(int idx, uint64_t val) { - assert(amu_supported()); + assert(amu_supported() != 0); assert(idx >= 0 && idx < AMU_GROUP0_NR_COUNTERS); amu_group0_cnt_write_internal(idx, val); @@ -73,7 +73,7 @@ void amu_group0_cnt_write(int idx, uint64_t val) /* Read the group 1 counter identified by the given `idx`. */ uint64_t amu_group1_cnt_read(int idx) { - assert(amu_supported()); + assert(amu_supported() != 0); assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS); return amu_group1_cnt_read_internal(idx); @@ -82,7 +82,7 @@ uint64_t amu_group1_cnt_read(int idx) /* Write the group 1 counter identified by the given `idx` with `val`. */ void amu_group1_cnt_write(int idx, uint64_t val) { - assert(amu_supported()); + assert(amu_supported() != 0); assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS); amu_group1_cnt_write_internal(idx, val); @@ -91,7 +91,7 @@ void amu_group1_cnt_write(int idx, uint64_t val) void amu_group1_set_evtype(int idx, unsigned int val) { - assert(amu_supported()); + assert(amu_supported() != 0); assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS); amu_group1_set_evtype_internal(idx, val); @@ -103,13 +103,14 @@ static void *amu_context_save(const void *arg) struct amu_ctx *ctx; int i; - if (!amu_supported()) + if (amu_supported() == 0) return (void *)-1; ctx = &amu_ctxs[plat_my_core_pos()]; /* Assert that group 0 counter configuration is what we expect */ - assert(read_amcntenset0() == AMU_GROUP0_COUNTERS_MASK); + assert(read_amcntenset0() == AMU_GROUP0_COUNTERS_MASK && + read_amcntenset1() == AMU_GROUP1_COUNTERS_MASK); /* * Disable group 0 counters to avoid other observers like SCP sampling @@ -131,17 +132,15 @@ static void *amu_context_save(const void *arg) static void *amu_context_restore(const void *arg) { struct amu_ctx *ctx; - uint64_t features; int i; - features = read_id_pfr0() >> ID_PFR0_AMU_SHIFT; - if ((features & ID_PFR0_AMU_MASK) != 1) + if (amu_supported() == 0) return (void *)-1; ctx = &amu_ctxs[plat_my_core_pos()]; /* Counters were disabled in `amu_context_save()` */ - assert(read_amcntenset0() == 0); + assert(read_amcntenset0() == 0 && read_amcntenset1() == 0); /* Restore group 0 counters */ for (i = 0; i < AMU_GROUP0_NR_COUNTERS; i++) diff --git a/lib/extensions/amu/aarch32/amu_helpers.S b/lib/extensions/amu/aarch32/amu_helpers.S index 84dca04c..effb8e50 100644 --- a/lib/extensions/amu/aarch32/amu_helpers.S +++ b/lib/extensions/amu/aarch32/amu_helpers.S @@ -18,7 +18,7 @@ * uint64_t amu_group0_cnt_read_internal(int idx); * * Given `idx`, read the corresponding AMU counter - * and return it in `r0`. + * and return it in `r0` and `r1`. */ func amu_group0_cnt_read_internal #if ENABLE_ASSERTIONS @@ -52,13 +52,15 @@ endfunc amu_group0_cnt_read_internal * void amu_group0_cnt_write_internal(int idx, uint64_t val); * * Given `idx`, write `val` to the corresponding AMU counter. + * `idx` is passed in `r0` and `val` is passed in `r2` and `r3`. + * `r1` is used as a scratch register. */ func amu_group0_cnt_write_internal #if ENABLE_ASSERTIONS /* `idx` should be between [0, 3] */ - mov r2, r0 - lsr r2, r2, #2 - cmp r2, #0 + mov r1, r0 + lsr r1, r1, #2 + cmp r1, #0 ASM_ASSERT(eq) #endif @@ -66,19 +68,19 @@ func amu_group0_cnt_write_internal * Given `idx` calculate address of stcopr16/bx lr instruction pair * in the table below. */ - adr r2, 1f + adr r1, 1f lsl r0, r0, #3 /* each stcopr16/bx lr sequence is 8 bytes */ - add r2, r2, r0 - bx r2 + add r1, r1, r0 + bx r1 1: - stcopr16 r0,r1, AMEVCNTR00 /* index 0 */ + stcopr16 r2, r3, AMEVCNTR00 /* index 0 */ bx lr - stcopr16 r0,r1, AMEVCNTR01 /* index 1 */ + stcopr16 r2, r3, AMEVCNTR01 /* index 1 */ bx lr - stcopr16 r0,r1, AMEVCNTR02 /* index 2 */ + stcopr16 r2, r3, AMEVCNTR02 /* index 2 */ bx lr - stcopr16 r0,r1, AMEVCNTR03 /* index 3 */ + stcopr16 r2, r3, AMEVCNTR03 /* index 3 */ bx lr endfunc amu_group0_cnt_write_internal @@ -86,14 +88,14 @@ endfunc amu_group0_cnt_write_internal * uint64_t amu_group1_cnt_read_internal(int idx); * * Given `idx`, read the corresponding AMU counter - * and return it in `r0`. + * and return it in `r0` and `r1`. */ func amu_group1_cnt_read_internal #if ENABLE_ASSERTIONS /* `idx` should be between [0, 15] */ - mov r2, r0 - lsr r2, r2, #4 - cmp r2, #0 + mov r1, r0 + lsr r1, r1, #4 + cmp r1, #0 ASM_ASSERT(eq) #endif @@ -107,51 +109,53 @@ func amu_group1_cnt_read_internal bx r1 1: - ldcopr16 r0,r1, AMEVCNTR10 /* index 0 */ - bx lr - ldcopr16 r0,r1, AMEVCNTR11 /* index 1 */ - bx lr - ldcopr16 r0,r1, AMEVCNTR12 /* index 2 */ - bx lr - ldcopr16 r0,r1, AMEVCNTR13 /* index 3 */ - bx lr - ldcopr16 r0,r1, AMEVCNTR14 /* index 4 */ - bx lr - ldcopr16 r0,r1, AMEVCNTR15 /* index 5 */ - bx lr - ldcopr16 r0,r1, AMEVCNTR16 /* index 6 */ - bx lr - ldcopr16 r0,r1, AMEVCNTR17 /* index 7 */ - bx lr - ldcopr16 r0,r1, AMEVCNTR18 /* index 8 */ - bx lr - ldcopr16 r0,r1, AMEVCNTR19 /* index 9 */ - bx lr - ldcopr16 r0,r1, AMEVCNTR1A /* index 10 */ - bx lr - ldcopr16 r0,r1, AMEVCNTR1B /* index 11 */ - bx lr - ldcopr16 r0,r1, AMEVCNTR1C /* index 12 */ - bx lr - ldcopr16 r0,r1, AMEVCNTR1D /* index 13 */ - bx lr - ldcopr16 r0,r1, AMEVCNTR1E /* index 14 */ - bx lr - ldcopr16 r0,r1, AMEVCNTR1F /* index 15 */ - bx lr + ldcopr16 r0, r1, AMEVCNTR10 /* index 0 */ + bx lr + ldcopr16 r0, r1, AMEVCNTR11 /* index 1 */ + bx lr + ldcopr16 r0, r1, AMEVCNTR12 /* index 2 */ + bx lr + ldcopr16 r0, r1, AMEVCNTR13 /* index 3 */ + bx lr + ldcopr16 r0, r1, AMEVCNTR14 /* index 4 */ + bx lr + ldcopr16 r0, r1, AMEVCNTR15 /* index 5 */ + bx lr + ldcopr16 r0, r1, AMEVCNTR16 /* index 6 */ + bx lr + ldcopr16 r0, r1, AMEVCNTR17 /* index 7 */ + bx lr + ldcopr16 r0, r1, AMEVCNTR18 /* index 8 */ + bx lr + ldcopr16 r0, r1, AMEVCNTR19 /* index 9 */ + bx lr + ldcopr16 r0, r1, AMEVCNTR1A /* index 10 */ + bx lr + ldcopr16 r0, r1, AMEVCNTR1B /* index 11 */ + bx lr + ldcopr16 r0, r1, AMEVCNTR1C /* index 12 */ + bx lr + ldcopr16 r0, r1, AMEVCNTR1D /* index 13 */ + bx lr + ldcopr16 r0, r1, AMEVCNTR1E /* index 14 */ + bx lr + ldcopr16 r0, r1, AMEVCNTR1F /* index 15 */ + bx lr endfunc amu_group1_cnt_read_internal /* * void amu_group1_cnt_write_internal(int idx, uint64_t val); * * Given `idx`, write `val` to the corresponding AMU counter. + * `idx` is passed in `r0` and `val` is passed in `r2` and `r3`. + * `r1` is used as a scratch register. */ func amu_group1_cnt_write_internal #if ENABLE_ASSERTIONS /* `idx` should be between [0, 15] */ - mov r2, r0 - lsr r2, r2, #4 - cmp r2, #0 + mov r1, r0 + lsr r1, r1, #4 + cmp r1, #0 ASM_ASSERT(eq) #endif @@ -159,43 +163,43 @@ func amu_group1_cnt_write_internal * Given `idx` calculate address of ldcopr16/bx lr instruction pair * in the table below. */ - adr r2, 1f + adr r1, 1f lsl r0, r0, #3 /* each stcopr16/bx lr sequence is 8 bytes */ - add r2, r2, r0 - bx r2 + add r1, r1, r0 + bx r1 1: - stcopr16 r0,r1, AMEVCNTR10 /* index 0 */ + stcopr16 r2, r3, AMEVCNTR10 /* index 0 */ bx lr - stcopr16 r0,r1, AMEVCNTR11 /* index 1 */ + stcopr16 r2, r3, AMEVCNTR11 /* index 1 */ bx lr - stcopr16 r0,r1, AMEVCNTR12 /* index 2 */ + stcopr16 r2, r3, AMEVCNTR12 /* index 2 */ bx lr - stcopr16 r0,r1, AMEVCNTR13 /* index 3 */ + stcopr16 r2, r3, AMEVCNTR13 /* index 3 */ bx lr - stcopr16 r0,r1, AMEVCNTR14 /* index 4 */ + stcopr16 r2, r3, AMEVCNTR14 /* index 4 */ bx lr - stcopr16 r0,r1, AMEVCNTR15 /* index 5 */ + stcopr16 r2, r3, AMEVCNTR15 /* index 5 */ bx lr - stcopr16 r0,r1, AMEVCNTR16 /* index 6 */ + stcopr16 r2, r3, AMEVCNTR16 /* index 6 */ bx lr - stcopr16 r0,r1, AMEVCNTR17 /* index 7 */ + stcopr16 r2, r3, AMEVCNTR17 /* index 7 */ bx lr - stcopr16 r0,r1, AMEVCNTR18 /* index 8 */ + stcopr16 r2, r3, AMEVCNTR18 /* index 8 */ bx lr - stcopr16 r0,r1, AMEVCNTR19 /* index 9 */ + stcopr16 r2, r3, AMEVCNTR19 /* index 9 */ bx lr - stcopr16 r0,r1, AMEVCNTR1A /* index 10 */ + stcopr16 r2, r3, AMEVCNTR1A /* index 10 */ bx lr - stcopr16 r0,r1, AMEVCNTR1B /* index 11 */ + stcopr16 r2, r3, AMEVCNTR1B /* index 11 */ bx lr - stcopr16 r0,r1, AMEVCNTR1C /* index 12 */ + stcopr16 r2, r3, AMEVCNTR1C /* index 12 */ bx lr - stcopr16 r0,r1, AMEVCNTR1D /* index 13 */ + stcopr16 r2, r3, AMEVCNTR1D /* index 13 */ bx lr - stcopr16 r0,r1, AMEVCNTR1E /* index 14 */ + stcopr16 r2, r3, AMEVCNTR1E /* index 14 */ bx lr - stcopr16 r0,r1, AMEVCNTR1F /* index 15 */ + stcopr16 r2, r3, AMEVCNTR1F /* index 15 */ bx lr endfunc amu_group1_cnt_write_internal @@ -230,36 +234,36 @@ func amu_group1_set_evtype_internal bx r2 1: - stcopr r0, AMEVTYPER10 /* index 0 */ + stcopr r1, AMEVTYPER10 /* index 0 */ bx lr - stcopr r0, AMEVTYPER11 /* index 1 */ + stcopr r1, AMEVTYPER11 /* index 1 */ bx lr - stcopr r0, AMEVTYPER12 /* index 2 */ + stcopr r1, AMEVTYPER12 /* index 2 */ bx lr - stcopr r0, AMEVTYPER13 /* index 3 */ + stcopr r1, AMEVTYPER13 /* index 3 */ bx lr - stcopr r0, AMEVTYPER14 /* index 4 */ + stcopr r1, AMEVTYPER14 /* index 4 */ bx lr - stcopr r0, AMEVTYPER15 /* index 5 */ + stcopr r1, AMEVTYPER15 /* index 5 */ bx lr - stcopr r0, AMEVTYPER16 /* index 6 */ + stcopr r1, AMEVTYPER16 /* index 6 */ bx lr - stcopr r0, AMEVTYPER17 /* index 7 */ + stcopr r1, AMEVTYPER17 /* index 7 */ bx lr - stcopr r0, AMEVTYPER18 /* index 8 */ + stcopr r1, AMEVTYPER18 /* index 8 */ bx lr - stcopr r0, AMEVTYPER19 /* index 9 */ + stcopr r1, AMEVTYPER19 /* index 9 */ bx lr - stcopr r0, AMEVTYPER1A /* index 10 */ + stcopr r1, AMEVTYPER1A /* index 10 */ bx lr - stcopr r0, AMEVTYPER1B /* index 11 */ + stcopr r1, AMEVTYPER1B /* index 11 */ bx lr - stcopr r0, AMEVTYPER1C /* index 12 */ + stcopr r1, AMEVTYPER1C /* index 12 */ bx lr - stcopr r0, AMEVTYPER1D /* index 13 */ + stcopr r1, AMEVTYPER1D /* index 13 */ bx lr - stcopr r0, AMEVTYPER1E /* index 14 */ + stcopr r1, AMEVTYPER1E /* index 14 */ bx lr - stcopr r0, AMEVTYPER1F /* index 15 */ + stcopr r1, AMEVTYPER1F /* index 15 */ bx lr endfunc amu_group1_set_evtype_internal diff --git a/lib/extensions/amu/aarch64/amu.c b/lib/extensions/amu/aarch64/amu.c index 7d39f35c..5d556e5d 100644 --- a/lib/extensions/amu/aarch64/amu.c +++ b/lib/extensions/amu/aarch64/amu.c @@ -37,7 +37,7 @@ void amu_enable(int el2_unused) { uint64_t v; - if (!amu_supported()) + if (amu_supported() == 0) return; if (el2_unused) { @@ -67,7 +67,7 @@ void amu_enable(int el2_unused) /* Read the group 0 counter identified by the given `idx`. */ uint64_t amu_group0_cnt_read(int idx) { - assert(amu_supported()); + assert(amu_supported() != 0); assert(idx >= 0 && idx < AMU_GROUP0_NR_COUNTERS); return amu_group0_cnt_read_internal(idx); @@ -76,7 +76,7 @@ uint64_t amu_group0_cnt_read(int idx) /* Write the group 0 counter identified by the given `idx` with `val`. */ void amu_group0_cnt_write(int idx, uint64_t val) { - assert(amu_supported()); + assert(amu_supported() != 0); assert(idx >= 0 && idx < AMU_GROUP0_NR_COUNTERS); amu_group0_cnt_write_internal(idx, val); @@ -86,7 +86,7 @@ void amu_group0_cnt_write(int idx, uint64_t val) /* Read the group 1 counter identified by the given `idx`. */ uint64_t amu_group1_cnt_read(int idx) { - assert(amu_supported()); + assert(amu_supported() != 0); assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS); return amu_group1_cnt_read_internal(idx); @@ -95,7 +95,7 @@ uint64_t amu_group1_cnt_read(int idx) /* Write the group 1 counter identified by the given `idx` with `val`. */ void amu_group1_cnt_write(int idx, uint64_t val) { - assert(amu_supported()); + assert(amu_supported() != 0); assert(idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS); amu_group1_cnt_write_internal(idx, val); @@ -108,7 +108,7 @@ void amu_group1_cnt_write(int idx, uint64_t val) */ void amu_group1_set_evtype(int idx, unsigned int val) { - assert(amu_supported()); + assert(amu_supported() != 0); assert (idx >= 0 && idx < AMU_GROUP1_NR_COUNTERS); amu_group1_set_evtype_internal(idx, val); @@ -120,7 +120,7 @@ static void *amu_context_save(const void *arg) struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()]; int i; - if (!amu_supported()) + if (amu_supported() == 0) return (void *)-1; /* Assert that group 0/1 counter configuration is what we expect */ @@ -154,7 +154,7 @@ static void *amu_context_restore(const void *arg) struct amu_ctx *ctx = &amu_ctxs[plat_my_core_pos()]; int i; - if (!amu_supported()) + if (amu_supported() == 0) return (void *)-1; /* Counters were disabled in `amu_context_save()` */ diff --git a/lib/extensions/spe/spe.c b/lib/extensions/spe/spe.c index 3b297f21..a9bed490 100644 --- a/lib/extensions/spe/spe.c +++ b/lib/extensions/spe/spe.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -14,71 +14,72 @@ */ #define psb_csync() asm volatile("hint #17") -void spe_enable(int el2_unused) +int spe_supported(void) { uint64_t features; features = read_id_aa64dfr0_el1() >> ID_AA64DFR0_PMS_SHIFT; - if ((features & ID_AA64DFR0_PMS_MASK) == 1) { - uint64_t v; + return (features & ID_AA64DFR0_PMS_MASK) == 1; +} - if (el2_unused) { - /* - * MDCR_EL2.TPMS (ARM v8.2): Do not trap statistical - * profiling controls to EL2. - * - * MDCR_EL2.E2PB (ARM v8.2): SPE enabled in Non-secure - * state. Accesses to profiling buffer controls at - * Non-secure EL1 are not trapped to EL2. - */ - v = read_mdcr_el2(); - v &= ~MDCR_EL2_TPMS; - v |= MDCR_EL2_E2PB(MDCR_EL2_E2PB_EL1); - write_mdcr_el2(v); - } +void spe_enable(int el2_unused) +{ + uint64_t v; + if (spe_supported() == 0) + return; + + if (el2_unused) { /* - * MDCR_EL2.NSPB (ARM v8.2): SPE enabled in Non-secure state - * and disabled in secure state. Accesses to SPE registers at - * S-EL1 generate trap exceptions to EL3. + * MDCR_EL2.TPMS (ARM v8.2): Do not trap statistical + * profiling controls to EL2. + * + * MDCR_EL2.E2PB (ARM v8.2): SPE enabled in Non-secure + * state. Accesses to profiling buffer controls at + * Non-secure EL1 are not trapped to EL2. */ - v = read_mdcr_el3(); - v |= MDCR_NSPB(MDCR_NSPB_EL1); - write_mdcr_el3(v); + v = read_mdcr_el2(); + v &= ~MDCR_EL2_TPMS; + v |= MDCR_EL2_E2PB(MDCR_EL2_E2PB_EL1); + write_mdcr_el2(v); } + + /* + * MDCR_EL2.NSPB (ARM v8.2): SPE enabled in Non-secure state + * and disabled in secure state. Accesses to SPE registers at + * S-EL1 generate trap exceptions to EL3. + */ + v = read_mdcr_el3(); + v |= MDCR_NSPB(MDCR_NSPB_EL1); + write_mdcr_el3(v); } void spe_disable(void) { - uint64_t features; + uint64_t v; - features = read_id_aa64dfr0_el1() >> ID_AA64DFR0_PMS_SHIFT; - if ((features & ID_AA64DFR0_PMS_MASK) == 1) { - uint64_t v; + if (spe_supported() == 0) + return; - /* Drain buffered data */ - psb_csync(); - dsbnsh(); + /* Drain buffered data */ + psb_csync(); + dsbnsh(); - /* Disable profiling buffer */ - v = read_pmblimitr_el1(); - v &= ~(1ULL << 0); - write_pmblimitr_el1(v); - isb(); - } + /* Disable profiling buffer */ + v = read_pmblimitr_el1(); + v &= ~(1ULL << 0); + write_pmblimitr_el1(v); + isb(); } static void *spe_drain_buffers_hook(const void *arg) { - uint64_t features; - - features = read_id_aa64dfr0_el1() >> ID_AA64DFR0_PMS_SHIFT; - if ((features & ID_AA64DFR0_PMS_MASK) == 1) { - /* Drain buffered data */ - psb_csync(); - dsbnsh(); - } + if (spe_supported() == 0) + return (void *)-1; + /* Drain buffered data */ + psb_csync(); + dsbnsh(); return 0; } diff --git a/lib/extensions/sve/sve.c b/lib/extensions/sve/sve.c index 14e51bd8..64424878 100644 --- a/lib/extensions/sve/sve.c +++ b/lib/extensions/sve/sve.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -9,117 +9,120 @@ #include <pubsub.h> #include <sve.h> -static void *disable_sve_hook(const void *arg) +int sve_supported(void) { uint64_t features; features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT; - if ((features & ID_AA64PFR0_SVE_MASK) == 1) { - uint64_t cptr; - - /* - * Disable SVE, SIMD and FP access for the Secure world. - * As the SIMD/FP registers are part of the SVE Z-registers, any - * use of SIMD/FP functionality will corrupt the SVE registers. - * Therefore it is necessary to prevent use of SIMD/FP support - * in the Secure world as well as SVE functionality. - */ - cptr = read_cptr_el3(); - cptr = (cptr | TFP_BIT) & ~(CPTR_EZ_BIT); - write_cptr_el3(cptr); + return (features & ID_AA64PFR0_SVE_MASK) == 1; +} - /* - * No explicit ISB required here as ERET to switch to Secure - * world covers it - */ - } +static void *disable_sve_hook(const void *arg) +{ + uint64_t cptr; + + if (sve_supported() == 0) + return (void *)-1; + + /* + * Disable SVE, SIMD and FP access for the Secure world. + * As the SIMD/FP registers are part of the SVE Z-registers, any + * use of SIMD/FP functionality will corrupt the SVE registers. + * Therefore it is necessary to prevent use of SIMD/FP support + * in the Secure world as well as SVE functionality. + */ + cptr = read_cptr_el3(); + cptr = (cptr | TFP_BIT) & ~(CPTR_EZ_BIT); + write_cptr_el3(cptr); + + /* + * No explicit ISB required here as ERET to switch to Secure + * world covers it + */ return 0; } static void *enable_sve_hook(const void *arg) { - uint64_t features; - - features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT; - if ((features & ID_AA64PFR0_SVE_MASK) == 1) { - uint64_t cptr; - - /* - * Enable SVE, SIMD and FP access for the Non-secure world. - */ - cptr = read_cptr_el3(); - cptr = (cptr | CPTR_EZ_BIT) & ~(TFP_BIT); - write_cptr_el3(cptr); - - /* - * No explicit ISB required here as ERET to switch to Non-secure - * world covers it - */ - } + uint64_t cptr; + + if (sve_supported() == 0) + return (void *)-1; + + /* + * Enable SVE, SIMD and FP access for the Non-secure world. + */ + cptr = read_cptr_el3(); + cptr = (cptr | CPTR_EZ_BIT) & ~(TFP_BIT); + write_cptr_el3(cptr); + + /* + * No explicit ISB required here as ERET to switch to Non-secure + * world covers it + */ return 0; } void sve_enable(int el2_unused) { - uint64_t features; + uint64_t cptr; + + if (sve_supported() == 0) + return; - features = read_id_aa64pfr0_el1() >> ID_AA64PFR0_SVE_SHIFT; - if ((features & ID_AA64PFR0_SVE_MASK) == 1) { - uint64_t cptr; #if CTX_INCLUDE_FPREGS - /* - * CTX_INCLUDE_FPREGS is not supported on SVE enabled systems. - */ - assert(0); + /* + * CTX_INCLUDE_FPREGS is not supported on SVE enabled systems. + */ + assert(0); #endif + /* + * Update CPTR_EL3 to enable access to SVE functionality for the + * Non-secure world. + * NOTE - assumed that CPTR_EL3.TFP is set to allow access to + * the SIMD, floating-point and SVE support. + * + * CPTR_EL3.EZ: Set to 1 to enable access to SVE functionality + * in the Non-secure world. + */ + cptr = read_cptr_el3(); + cptr |= CPTR_EZ_BIT; + write_cptr_el3(cptr); + + /* + * Need explicit ISB here to guarantee that update to ZCR_ELx + * and CPTR_EL2.TZ do not result in trap to EL3. + */ + isb(); + + /* + * Ensure lower ELs have access to full vector length. + */ + write_zcr_el3(ZCR_EL3_LEN_MASK); + + if (el2_unused) { /* - * Update CPTR_EL3 to enable access to SVE functionality for the - * Non-secure world. - * NOTE - assumed that CPTR_EL3.TFP is set to allow access to - * the SIMD, floating-point and SVE support. + * Update CPTR_EL2 to enable access to SVE functionality + * for Non-secure world, EL2 and Non-secure EL1 and EL0. + * NOTE - assumed that CPTR_EL2.TFP is set to allow + * access to the SIMD, floating-point and SVE support. * - * CPTR_EL3.EZ: Set to 1 to enable access to SVE functionality - * in the Non-secure world. + * CPTR_EL2.TZ: Set to 0 to enable access to SVE support + * for EL2 and Non-secure EL1 and EL0. */ - cptr = read_cptr_el3(); - cptr |= CPTR_EZ_BIT; - write_cptr_el3(cptr); - - /* - * Need explicit ISB here to guarantee that update to ZCR_ELx - * and CPTR_EL2.TZ do not result in trap to EL3. - */ - isb(); + cptr = read_cptr_el2(); + cptr &= ~(CPTR_EL2_TZ_BIT); + write_cptr_el2(cptr); /* * Ensure lower ELs have access to full vector length. */ - write_zcr_el3(ZCR_EL3_LEN_MASK); - - if (el2_unused) { - /* - * Update CPTR_EL2 to enable access to SVE functionality - * for Non-secure world, EL2 and Non-secure EL1 and EL0. - * NOTE - assumed that CPTR_EL2.TFP is set to allow - * access to the SIMD, floating-point and SVE support. - * - * CPTR_EL2.TZ: Set to 0 to enable access to SVE support - * for EL2 and Non-secure EL1 and EL0. - */ - cptr = read_cptr_el2(); - cptr &= ~(CPTR_EL2_TZ_BIT); - write_cptr_el2(cptr); - - /* - * Ensure lower ELs have access to full vector length. - */ - write_zcr_el2(ZCR_EL2_LEN_MASK); - } - /* - * No explicit ISB required here as ERET to switch to - * Non-secure world covers it. - */ + write_zcr_el2(ZCR_EL2_LEN_MASK); } + /* + * No explicit ISB required here as ERET to switch to + * Non-secure world covers it. + */ } SUBSCRIBE_TO_EVENT(cm_exited_normal_world, disable_sve_hook); diff --git a/make_helpers/build_macros.mk b/make_helpers/build_macros.mk index 9119dcd2..eba9168c 100644 --- a/make_helpers/build_macros.mk +++ b/make_helpers/build_macros.mk @@ -344,15 +344,18 @@ $(if $(2),$(call TOOL_ADD_IMG_PAYLOAD,bl$(1),$(BIN),--$(2),$(BIN),$(3))) endef +# Convert device tree source file names to matching blobs +# $(1) = input dts define SOURCES_TO_DTBS $(notdir $(patsubst %.dts,%.dtb,$(filter %.dts,$(1)))) endef -# MAKE_FDT macro defines the targets and options to build each FDT binary -# Arguments: (none) -define MAKE_FDT - $(eval DTB_BUILD_DIR := ${BUILD_PLAT}/fdts) - $(eval DTBS := $(addprefix $(DTB_BUILD_DIR)/,$(call SOURCES_TO_DTBS,$(FDT_SOURCES)))) +# MAKE_FDT_DIRS macro creates the prerequisite directories that host the +# FDT binaries +# $(1) = output directory +# $(2) = input dts +define MAKE_FDT_DIRS + $(eval DTBS := $(addprefix $(1)/,$(call SOURCES_TO_DTBS,$(2)))) $(eval TEMP_DTB_DIRS := $(sort $(dir ${DTBS}))) # The $(dir ) function leaves a trailing / on the directory names # Rip off the / to match directory names with make rule targets. @@ -361,19 +364,18 @@ define MAKE_FDT $(eval $(foreach objd,${DTB_DIRS},$(call MAKE_PREREQ_DIR,${objd},${BUILD_DIR}))) fdt_dirs: ${DTB_DIRS} - endef -# MAKE_DTB generate the Flattened device tree binary (device tree binary) +# MAKE_DTB generate the Flattened device tree binary # $(1) = output directory # $(2) = input dts define MAKE_DTB -$(eval DOBJ := $(1)/$(patsubst %.dts,%.dtb,$(notdir $(2)))) +$(eval DOBJ := $(addprefix $(1)/,$(call SOURCES_TO_DTBS,$(2)))) $(eval DEP := $(patsubst %.dtb,%.d,$(DOBJ))) $(DOBJ): $(2) $(MAKEFILE_LIST) | fdt_dirs - @echo " DTC $$<" + @echo " DTC $$<" $$(Q)$$(DTC) $$(DTC_FLAGS) -d $(DEP) -o $$@ $$< -include $(DEP) @@ -386,7 +388,11 @@ endef define MAKE_DTBS $(eval DOBJS := $(filter %.dts,$(2))) $(eval REMAIN := $(filter-out %.dts,$(2))) + $(and $(REMAIN),$(error FDT_SOURCES contain non-DTS files: $(REMAIN))) $(eval $(foreach obj,$(DOBJS),$(call MAKE_DTB,$(1),$(obj)))) - $(and $(REMAIN),$(error Unexpected s present: $(REMAIN))) + $(eval $(call MAKE_FDT_DIRS,$(1),$(2))) + +dtbs: $(DTBS) +all: dtbs endef diff --git a/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts b/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts new file mode 100644 index 00000000..5c24f94e --- /dev/null +++ b/plat/arm/board/fvp/fdts/fvp_tb_fw_config.dts @@ -0,0 +1,16 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +/dts-v1/; + +/ { + /* Platform Config */ + plat_arm_bl2 { + compatible = "arm,tb_fw"; + hw_config_addr = <0x0 0x82000000>; + hw_config_max_size = <0x01000000>; + }; +}; diff --git a/plat/arm/board/fvp/fvp_bl2_setup.c b/plat/arm/board/fvp/fvp_bl2_setup.c index e9c4ab5c..0a3b67d3 100644 --- a/plat/arm/board/fvp/fvp_bl2_setup.c +++ b/plat/arm/board/fvp/fvp_bl2_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,15 +7,15 @@ #include <generic_delay_timer.h> #include <mmio.h> #include <plat_arm.h> +#include <platform.h> #include <sp804_delay_timer.h> #include <v2m_def.h> #include "fvp_def.h" #include "fvp_private.h" - -void bl2_early_platform_setup(meminfo_t *mem_layout) +void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { - arm_bl2_early_platform_setup(mem_layout); + arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); /* Initialize the platform config for future decision making */ fvp_config_setup(); diff --git a/plat/arm/board/fvp/fvp_bl31_setup.c b/plat/arm/board/fvp/fvp_bl31_setup.c index 181c9231..bcba60a3 100644 --- a/plat/arm/board/fvp/fvp_bl31_setup.c +++ b/plat/arm/board/fvp/fvp_bl31_setup.c @@ -1,23 +1,19 @@ /* - * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <arm_config.h> #include <plat_arm.h> +#include <platform.h> #include <smmu_v3.h> #include "fvp_private.h" -#if LOAD_IMAGE_V2 -void bl31_early_platform_setup(void *from_bl2, - void *plat_params_from_bl2) -#else -void bl31_early_platform_setup(bl31_params_t *from_bl2, - void *plat_params_from_bl2) -#endif +void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) { - arm_bl31_early_platform_setup(from_bl2, plat_params_from_bl2); + arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); /* Initialize the platform config for future decision making */ fvp_config_setup(); diff --git a/plat/arm/board/fvp/fvp_io_storage.c b/plat/arm/board/fvp/fvp_io_storage.c index aa2ee305..11c7c3bc 100644 --- a/plat/arm/board/fvp/fvp_io_storage.c +++ b/plat/arm/board/fvp/fvp_io_storage.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,6 +18,8 @@ #define BL31_IMAGE_NAME "bl31.bin" #define BL32_IMAGE_NAME "bl32.bin" #define BL33_IMAGE_NAME "bl33.bin" +#define TB_FW_CONFIG_NAME "fvp_tb_fw_config.dtb" +#define HW_CONFIG_NAME "hw_config.dtb" #if TRUSTED_BOARD_BOOT #define TRUSTED_BOOT_FW_CERT_NAME "tb_fw.crt" @@ -51,6 +53,14 @@ static const io_file_spec_t sh_file_spec[] = { .path = BL33_IMAGE_NAME, .mode = FOPEN_MODE_RB }, + [TB_FW_CONFIG_ID] = { + .path = TB_FW_CONFIG_NAME, + .mode = FOPEN_MODE_RB + }, + [HW_CONFIG_ID] = { + .path = HW_CONFIG_NAME, + .mode = FOPEN_MODE_RB + }, #if TRUSTED_BOARD_BOOT [TRUSTED_BOOT_FW_CERT_ID] = { .path = TRUSTED_BOOT_FW_CERT_NAME, diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk index a257784c..8b913fb2 100644 --- a/plat/arm/board/fvp/platform.mk +++ b/plat/arm/board/fvp/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # @@ -16,6 +16,8 @@ FVP_CLUSTER_COUNT := 2 # Default number of threads per CPU on FVP FVP_MAX_PE_PER_CPU := 1 +FVP_DT_PREFIX := fvp-base-gicv3-psci + $(eval $(call assert_boolean,FVP_USE_SP804_TIMER)) $(eval $(call add_define,FVP_USE_SP804_TIMER)) @@ -59,6 +61,9 @@ FVP_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ drivers/arm/gic/v2/gicv2_helpers.c \ plat/common/plat_gicv2.c \ plat/arm/common/arm_gicv2.c + +FVP_DT_PREFIX := fvp-base-gicv2-psci + else ifeq (${FVP_USE_GIC_DRIVER}, FVP_GICV3_LEGACY) ifeq (${ARCH}, aarch32) $(error "GICV3 Legacy driver not supported for AArch32 build") @@ -68,6 +73,9 @@ FVP_GIC_SOURCES := drivers/arm/gic/arm_gic.c \ drivers/arm/gic/gic_v3.c \ plat/common/plat_gic.c \ plat/arm/common/arm_gicv3_legacy.c + +FVP_DT_PREFIX := fvp-base-gicv2-psci + else $(error "Incorrect GIC driver chosen on FVP port") endif @@ -151,6 +159,22 @@ BL31_SOURCES += drivers/arm/smmu/smmu_v3.c \ ${FVP_INTERCONNECT_SOURCES} \ ${FVP_SECURITY_SOURCES} +# Add the FDT_SOURCES and options for Dynamic Config (only for Unix env) +ifdef UNIX_MK +FVP_HW_CONFIG_DTS := fdts/${FVP_DT_PREFIX}.dts +FDT_SOURCES += plat/arm/board/fvp/fdts/${PLAT}_tb_fw_config.dts +FVP_TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb + +# Add the TB_FW_CONFIG to FIP and specify the same to certtool +$(eval $(call TOOL_ADD_PAYLOAD,${FVP_TB_FW_CONFIG},--tb-fw-config)) + +FDT_SOURCES += ${FVP_HW_CONFIG_DTS} +$(eval FVP_HW_CONFIG := ${BUILD_PLAT}/$(patsubst %.dts,%.dtb,$(FVP_HW_CONFIG_DTS))) + +# Add the HW_CONFIG to FIP and specify the same to certtool +$(eval $(call TOOL_ADD_PAYLOAD,${FVP_HW_CONFIG},--hw-config)) +endif + # Disable the PSCI platform compatibility layer ENABLE_PLAT_COMPAT := 0 @@ -158,7 +182,9 @@ ENABLE_PLAT_COMPAT := 0 ENABLE_AMU := 1 ifeq (${ENABLE_AMU},1) -BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c +BL31_SOURCES += lib/cpus/aarch64/cortex_a75_pubsub.c \ + lib/cpus/aarch64/cpuamu.c \ + lib/cpus/aarch64/cpuamu_helpers.S endif ifneq (${ENABLE_STACK_PROTECTOR},0) diff --git a/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c b/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c index b9246367..6cced4dd 100644 --- a/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c +++ b/plat/arm/board/fvp/sp_min/fvp_sp_min_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,10 +7,10 @@ #include <plat_arm.h> #include "../fvp_private.h" -void sp_min_early_platform_setup(void *from_bl2, - void *plat_params_from_bl2) +void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) { - arm_sp_min_early_platform_setup(from_bl2, plat_params_from_bl2); + arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); /* Initialize the platform config for future decision making */ fvp_config_setup(); diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h index cac47f72..2e2fdd7a 100644 --- a/plat/arm/board/juno/include/platform_def.h +++ b/plat/arm/board/juno/include/platform_def.h @@ -110,12 +110,12 @@ */ #if TRUSTED_BOARD_BOOT #if TF_MBEDTLS_KEY_ALG_ID == TF_MBEDTLS_RSA_AND_ECDSA -# define PLAT_ARM_MAX_BL2_SIZE 0x1E000 +# define PLAT_ARM_MAX_BL2_SIZE 0x1F000 #else -# define PLAT_ARM_MAX_BL2_SIZE 0x1A000 +# define PLAT_ARM_MAX_BL2_SIZE 0x1B000 #endif #else -# define PLAT_ARM_MAX_BL2_SIZE 0xC000 +# define PLAT_ARM_MAX_BL2_SIZE 0xD000 #endif /* diff --git a/plat/arm/common/aarch32/arm_bl2_mem_params_desc.c b/plat/arm/common/aarch32/arm_bl2_mem_params_desc.c index 7fd42aa1..890f2c96 100644 --- a/plat/arm/common/aarch32/arm_bl2_mem_params_desc.c +++ b/plat/arm/common/aarch32/arm_bl2_mem_params_desc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -54,7 +54,15 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { .next_handoff_image_id = BL33_IMAGE_ID, }, - + /* Fill HW_CONFIG related information if it exists */ + { + .image_id = HW_CONFIG_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_2, entry_point_info_t, NON_SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + .next_handoff_image_id = INVALID_IMAGE_ID, + }, /* Fill BL33 related information */ { .image_id = BL33_IMAGE_ID, diff --git a/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c b/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c index 4376119a..fef01c9d 100644 --- a/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c +++ b/plat/arm/common/aarch64/arm_bl2_mem_params_desc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -68,7 +68,7 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { .ep_info.spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS), #if DEBUG - .ep_info.args.arg1 = ARM_BL31_PLAT_PARAM_VAL, + .ep_info.args.arg3 = ARM_BL31_PLAT_PARAM_VAL, #endif SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, @@ -82,7 +82,15 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = { .next_handoff_image_id = BL33_IMAGE_ID, # endif }, - + /* Fill HW_CONFIG related information */ + { + .image_id = HW_CONFIG_ID, + SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, + VERSION_2, entry_point_info_t, NON_SECURE | NON_EXECUTABLE), + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_2, image_info_t, IMAGE_ATTRIB_SKIP_LOADING), + .next_handoff_image_id = INVALID_IMAGE_ID, + }, # ifdef BL32_BASE /* Fill BL32 related information */ { diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c index 6860e36b..0b9c9eef 100644 --- a/plat/arm/common/arm_bl1_setup.c +++ b/plat/arm/common/arm_bl1_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -115,6 +115,9 @@ void arm_bl1_platform_setup(void) { /* Initialise the IO layer and register platform IO devices */ plat_arm_io_setup(); +#if LOAD_IMAGE_V2 + arm_load_tb_fw_config(); +#endif } void bl1_platform_setup(void) diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c index 906ed197..7add61da 100644 --- a/plat/arm/common/arm_bl2_setup.c +++ b/plat/arm/common/arm_bl2_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -39,7 +39,7 @@ static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); CASSERT(BL2_BASE >= (ARM_BL_RAM_BASE + BL1_MEMINFO_OFFSET), assert_bl2_base_overflows); /* Weak definitions may be overridden in specific ARM standard platform */ -#pragma weak bl2_early_platform_setup +#pragma weak bl2_early_platform_setup2 #pragma weak bl2_platform_setup #pragma weak bl2_plat_arch_setup #pragma weak bl2_plat_sec_mem_layout @@ -169,7 +169,7 @@ void bl2_plat_flush_bl31_params(void) struct entry_point_info *bl2_plat_get_bl31_ep_info(void) { #if DEBUG - bl31_params_mem.bl31_ep_info.args.arg1 = ARM_BL31_PLAT_PARAM_VAL; + bl31_params_mem.bl31_ep_info.args.arg3 = ARM_BL31_PLAT_PARAM_VAL; #endif return &bl31_params_mem.bl31_ep_info; @@ -181,7 +181,7 @@ struct entry_point_info *bl2_plat_get_bl31_ep_info(void) * in x0. This memory layout is sitting at the base of the free trusted SRAM. * Copy it to a safe location before its reclaimed by later BL2 functionality. ******************************************************************************/ -void arm_bl2_early_platform_setup(meminfo_t *mem_layout) +void arm_bl2_early_platform_setup(uintptr_t tb_fw_config, meminfo_t *mem_layout) { /* Initialize the console to provide early debug support */ console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, @@ -192,11 +192,17 @@ void arm_bl2_early_platform_setup(meminfo_t *mem_layout) /* Initialise the IO layer and register platform IO devices */ plat_arm_io_setup(); + +#if LOAD_IMAGE_V2 + if (tb_fw_config != 0U) + arm_bl2_set_tb_cfg_addr((void *)tb_fw_config); +#endif } -void bl2_early_platform_setup(meminfo_t *mem_layout) +void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, u_register_t arg2, u_register_t arg3) { - arm_bl2_early_platform_setup(mem_layout); + arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); + generic_delay_timer_init(); } @@ -205,6 +211,10 @@ void bl2_early_platform_setup(meminfo_t *mem_layout) */ void arm_bl2_platform_setup(void) { +#if LOAD_IMAGE_V2 + arm_bl2_dyn_cfg_init(); +#endif + /* Initialize the secure environment */ plat_arm_security_setup(); diff --git a/plat/arm/common/arm_bl31_setup.c b/plat/arm/common/arm_bl31_setup.c index 8fba80b1..963c4d2b 100644 --- a/plat/arm/common/arm_bl31_setup.c +++ b/plat/arm/common/arm_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -26,7 +26,7 @@ static entry_point_info_t bl33_image_ep_info; /* Weak definitions may be overridden in specific ARM standard platform */ -#pragma weak bl31_early_platform_setup +#pragma weak bl31_early_platform_setup2 #pragma weak bl31_platform_setup #pragma weak bl31_plat_arch_setup #pragma weak bl31_plat_get_next_image_ep_info @@ -64,11 +64,11 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) * we are guaranteed to pick up good data. ******************************************************************************/ #if LOAD_IMAGE_V2 -void arm_bl31_early_platform_setup(void *from_bl2, - void *plat_params_from_bl2) +void arm_bl31_early_platform_setup(void *from_bl2, uintptr_t soc_fw_config, + uintptr_t hw_config, void *plat_params_from_bl2) #else -void arm_bl31_early_platform_setup(bl31_params_t *from_bl2, - void *plat_params_from_bl2) +void arm_bl31_early_platform_setup(bl31_params_t *from_bl2, uintptr_t soc_fw_config, + uintptr_t hw_config, void *plat_params_from_bl2) #endif { /* Initialize the console to provide early debug support */ @@ -152,6 +152,10 @@ void arm_bl31_early_platform_setup(bl31_params_t *from_bl2, assert(from_bl2->h.type == PARAM_BL31); assert(from_bl2->h.version >= VERSION_1); + /* Dynamic Config is not supported for LOAD_IMAGE_V1 */ + assert(soc_fw_config == 0); + assert(hw_config == 0); + /* * Copy BL32 (if populated by BL2) and BL33 entry point information. * They are stored in Secure RAM, in BL2's address space. @@ -164,15 +168,10 @@ void arm_bl31_early_platform_setup(bl31_params_t *from_bl2, #endif /* RESET_TO_BL31 */ } -#if LOAD_IMAGE_V2 -void bl31_early_platform_setup(void *from_bl2, - void *plat_params_from_bl2) -#else -void bl31_early_platform_setup(bl31_params_t *from_bl2, - void *plat_params_from_bl2) -#endif +void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) { - arm_bl31_early_platform_setup(from_bl2, plat_params_from_bl2); + arm_bl31_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); /* * Initialize Interconnect for this cluster during cold boot. diff --git a/plat/arm/common/arm_common.mk b/plat/arm/common/arm_common.mk index 48e70717..b3462ab8 100644 --- a/plat/arm/common/arm_common.mk +++ b/plat/arm/common/arm_common.mk @@ -136,6 +136,7 @@ BL1_SOURCES += drivers/arm/sp805/sp805.c \ drivers/io/io_memmap.c \ drivers/io/io_storage.c \ plat/arm/common/arm_bl1_setup.c \ + plat/arm/common/arm_dyn_cfg.c \ plat/arm/common/arm_io_storage.c ifdef EL3_PAYLOAD_BASE # Need the arm_program_trusted_mailbox() function to release secondary CPUs from @@ -151,6 +152,13 @@ BL2_SOURCES += drivers/delay_timer/delay_timer.c \ plat/arm/common/arm_bl2_setup.c \ plat/arm/common/arm_io_storage.c +# Add `libfdt` and Arm common helpers required for Dynamic Config +include lib/libfdt/libfdt.mk +BL2_SOURCES += plat/arm/common/arm_dyn_cfg.c \ + plat/arm/common/arm_dyn_cfg_helpers.c \ + common/fdt_wrappers.c \ + ${LIBFDT_SRCS} + ifeq (${BL2_AT_EL3},1) BL2_SOURCES += plat/arm/common/arm_bl2_el3_setup.c endif diff --git a/plat/arm/common/arm_dyn_cfg.c b/plat/arm/common/arm_dyn_cfg.c new file mode 100644 index 00000000..02f995f7 --- /dev/null +++ b/plat/arm/common/arm_dyn_cfg.c @@ -0,0 +1,109 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arm_dyn_cfg_helpers.h> +#include <assert.h> +#include <debug.h> +#include <desc_image_load.h> +#include <plat_arm.h> +#include <platform.h> +#include <platform_def.h> +#include <string.h> +#include <tbbr_img_def.h> + +#if LOAD_IMAGE_V2 + +/* Variable to store the address to TB_FW_CONFIG passed from BL1 */ +static void *tb_fw_cfg_dtb; + +/* + * Helper function to load TB_FW_CONFIG and populate the load information to + * arg0 of BL2 entrypoint info. + */ +void arm_load_tb_fw_config(void) +{ + int err; + uintptr_t config_base = 0; + image_desc_t *image_desc; + + image_desc_t arm_tb_fw_info = { + .image_id = TB_FW_CONFIG_ID, + SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, + VERSION_2, image_info_t, 0), + .image_info.image_base = ARM_TB_FW_CONFIG_BASE, + .image_info.image_max_size = ARM_TB_FW_CONFIG_LIMIT - ARM_TB_FW_CONFIG_BASE, + }; + + VERBOSE("BL1: Loading TB_FW_CONFIG\n"); + err = load_auth_image(TB_FW_CONFIG_ID, &arm_tb_fw_info.image_info); + if (err != 0) { + /* Return if TB_FW_CONFIG is not loaded */ + VERBOSE("Failed to load TB_FW_CONFIG\n"); + return; + } + + config_base = arm_tb_fw_info.image_info.image_base; + + /* The BL2 ep_info arg0 is modified to point to TB_FW_CONFIG */ + image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID); + assert(image_desc != NULL); + image_desc->ep_info.args.arg0 = config_base; + + INFO("BL1: TB_FW_CONFIG loaded at address = %p\n", + (void *) config_base); +} + +/* + * BL2 utility function to set the address of TB_FW_CONFIG passed from BL1. + */ +void arm_bl2_set_tb_cfg_addr(void *dtb) +{ + assert(dtb != NULL); + tb_fw_cfg_dtb = dtb; +} + +/* + * BL2 utility function to initialize dynamic configuration specified by + * TB_FW_CONFIG. Return early if TB_FW_CONFIG is not found or HW_CONFIG is + * not specified in TB_FW_CONFIG. + */ +void arm_bl2_dyn_cfg_init(void) +{ + int err = 0; + int tb_fw_node; + bl_mem_params_node_t *hw_cfg_mem_params = NULL; + + if (tb_fw_cfg_dtb == NULL) { + VERBOSE("No TB_FW_CONFIG specified\n"); + return; + } + + err = arm_dyn_tb_fw_cfg_init((void *)tb_fw_cfg_dtb, &tb_fw_node); + if (err < 0) { + ERROR("Invalid TB_FW_CONFIG passed from BL1\n"); + panic(); + } + + /* Get the hw_config load address and size from TB_FW_CONFIG */ + hw_cfg_mem_params = get_bl_mem_params_node(HW_CONFIG_ID); + if (hw_cfg_mem_params == NULL) { + VERBOSE("Couldn't find HW_CONFIG in bl_mem_params_node\n"); + return; + } + + err = arm_dyn_get_hwconfig_info((void *)tb_fw_cfg_dtb, tb_fw_node, + (uint64_t *) &hw_cfg_mem_params->image_info.image_base, + &hw_cfg_mem_params->image_info.image_max_size); + if (err < 0) { + VERBOSE("Couldn't find HW_CONFIG load info in TB_FW_CONFIG\n"); + return; + } + + /* Remove the IMAGE_ATTRIB_SKIP_LOADING attribute from HW_CONFIG node */ + hw_cfg_mem_params->image_info.h.attr &= ~IMAGE_ATTRIB_SKIP_LOADING; +} + +#endif /* LOAD_IMAGE_V2 */ diff --git a/plat/arm/common/arm_dyn_cfg_helpers.c b/plat/arm/common/arm_dyn_cfg_helpers.c new file mode 100644 index 00000000..cfcbf2a2 --- /dev/null +++ b/plat/arm/common/arm_dyn_cfg_helpers.c @@ -0,0 +1,94 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <assert.h> +#include <desc_image_load.h> +#include <fdt_wrappers.h> +#include <libfdt.h> +#include <plat_arm.h> + +/******************************************************************************* + * Helper to read the `hw_config` property in config DTB. This function + * expects the following properties to be present in the config DTB. + * name : hw_config_addr size : 2 cells + * name : hw_config_max_size size : 1 cell + * + * Arguments: + * void *dtb - pointer to the TB_FW_CONFIG in memory + * int node - The node offset to appropriate node in the + * DTB. + * uint64_t *hw_config_addr - Returns the `hw_config` load address if read + * is successful. + * uint32_t *hw_config_size - Returns the `hw_config` size if read is + * successful. + * + * Returns 0 on success and -1 on error. + ******************************************************************************/ +int arm_dyn_get_hwconfig_info(void *dtb, int node, + uint64_t *hw_config_addr, uint32_t *hw_config_size) +{ + int err; + + assert(dtb != NULL); + assert(hw_config_addr != NULL); + assert(hw_config_size != NULL); + + /* Check if the pointer to DT is correct */ + assert(fdt_check_header(dtb) == 0); + + /* Assert the node offset point to "arm,tb_fw" compatible property */ + assert(node == fdt_node_offset_by_compatible(dtb, -1, "arm,tb_fw")); + + err = fdtw_read_cells(dtb, node, "hw_config_addr", 2, + (void *) hw_config_addr); + if (err < 0) { + WARN("Read cell failed for hw_config_addr\n"); + return -1; + } + + err = fdtw_read_cells(dtb, node, "hw_config_max_size", 1, + (void *) hw_config_size); + if (err < 0) { + WARN("Read cell failed for hw_config_max_size\n"); + return -1; + } + + VERBOSE("Dyn cfg: Read hw_config address from TB_FW_CONFIG 0x%p %p\n", + hw_config_addr, hw_config_size); + + return 0; +} + +/******************************************************************************* + * Validate the tb_fw_config is a valid DTB file and returns the node offset + * to "arm,tb_fw" property. + * Arguments: + * void *dtb - pointer to the TB_FW_CONFIG in memory + * int *node - Returns the node offset to "arm,tb_fw" property if found. + * + * Returns 0 on success and -1 on error. + ******************************************************************************/ +int arm_dyn_tb_fw_cfg_init(void *dtb, int *node) +{ + assert(dtb != NULL); + assert(node != NULL); + + /* Check if the pointer to DT is correct */ + if (fdt_check_header(dtb) != 0) { + WARN("Invalid DTB file passed as TB_FW_CONFIG\n"); + return -1; + } + + /* Assert the node offset point to "arm,tb_fw" compatible property */ + *node = fdt_node_offset_by_compatible(dtb, -1, "arm,tb_fw"); + if (*node < 0) { + WARN("The compatible property `arm,tb_fw` not found in the config\n"); + return -1; + } + + VERBOSE("Dyn cfg: Found \"arm,tb_fw\" in the config\n"); + return 0; +} diff --git a/plat/arm/common/arm_image_load.c b/plat/arm/common/arm_image_load.c index 03e4b4f4..916fa8dc 100644 --- a/plat/arm/common/arm_image_load.c +++ b/plat/arm/common/arm_image_load.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,6 +7,7 @@ #include <arm_def.h> #include <bl_common.h> #include <desc_image_load.h> +#include <plat_arm.h> #include <platform.h> @@ -37,5 +38,8 @@ bl_load_info_t *plat_get_bl_image_load_info(void) ******************************************************************************/ bl_params_t *plat_get_next_bl_params(void) { - return get_next_bl_params_from_mem_params_desc(); + bl_params_t *next_bl_params = get_next_bl_params_from_mem_params_desc(); + + populate_next_bl_params_config(next_bl_params); + return next_bl_params; } diff --git a/plat/arm/common/arm_io_storage.c b/plat/arm/common/arm_io_storage.c index 794ef619..5cabc546 100644 --- a/plat/arm/common/arm_io_storage.c +++ b/plat/arm/common/arm_io_storage.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -53,6 +53,14 @@ static const io_uuid_spec_t bl33_uuid_spec = { .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33, }; +static const io_uuid_spec_t tb_fw_config_uuid_spec = { + .uuid = UUID_TB_FW_CONFIG, +}; + +static const io_uuid_spec_t hw_config_uuid_spec = { + .uuid = UUID_HW_CONFIG, +}; + #if TRUSTED_BOARD_BOOT static const io_uuid_spec_t tb_fw_cert_uuid_spec = { .uuid = UUID_TRUSTED_BOOT_FW_CERT, @@ -147,6 +155,16 @@ static const struct plat_io_policy policies[] = { (uintptr_t)&bl33_uuid_spec, open_fip }, + [TB_FW_CONFIG_ID] = { + &fip_dev_handle, + (uintptr_t)&tb_fw_config_uuid_spec, + open_fip + }, + [HW_CONFIG_ID] = { + &fip_dev_handle, + (uintptr_t)&hw_config_uuid_spec, + open_fip + }, #if TRUSTED_BOARD_BOOT [TRUSTED_BOOT_FW_CERT_ID] = { &fip_dev_handle, diff --git a/plat/arm/common/sp_min/arm_sp_min_setup.c b/plat/arm/common/sp_min/arm_sp_min_setup.c index c5408c8f..1776d46a 100644 --- a/plat/arm/common/sp_min/arm_sp_min_setup.c +++ b/plat/arm/common/sp_min/arm_sp_min_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -18,7 +18,7 @@ static entry_point_info_t bl33_image_ep_info; /* Weak definitions may be overridden in specific ARM standard platform */ -#pragma weak sp_min_early_platform_setup +#pragma weak sp_min_early_platform_setup2 #pragma weak sp_min_platform_setup #pragma weak sp_min_plat_arch_setup @@ -48,8 +48,8 @@ entry_point_info_t *sp_min_plat_get_bl33_ep_info(void) /******************************************************************************* * Perform early platform setup. ******************************************************************************/ -void arm_sp_min_early_platform_setup(void *from_bl2, - void *plat_params_from_bl2) +void arm_sp_min_early_platform_setup(void *from_bl2, uintptr_t tos_fw_config, + uintptr_t hw_config, void *plat_params_from_bl2) { /* Initialize the console to provide early debug support */ console_init(PLAT_ARM_BOOT_UART_BASE, PLAT_ARM_BOOT_UART_CLK_IN_HZ, @@ -105,10 +105,10 @@ void arm_sp_min_early_platform_setup(void *from_bl2, } -void sp_min_early_platform_setup(void *from_bl2, - void *plat_params_from_bl2) +void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) { - arm_sp_min_early_platform_setup(from_bl2, plat_params_from_bl2); + arm_sp_min_early_platform_setup((void *)arg0, arg1, arg2, (void *)arg3); /* * Initialize Interconnect for this cluster during cold boot. diff --git a/plat/arm/css/common/css_bl2_setup.c b/plat/arm/css/common/css_bl2_setup.c index b4aafd46..33e7b2ef 100644 --- a/plat/arm/css/common/css_bl2_setup.c +++ b/plat/arm/css/common/css_bl2_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -60,9 +60,10 @@ int bl2_plat_handle_scp_bl2(image_info_t *scp_bl2_image_info) static unsigned int scp_boot_config; -void bl2_early_platform_setup(meminfo_t *mem_layout) +void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) { - arm_bl2_early_platform_setup(mem_layout); + arm_bl2_early_platform_setup((uintptr_t)arg0, (meminfo_t *)arg1); /* Save SCP Boot config before it gets overwritten by SCP_BL2 loading */ scp_boot_config = mmio_read_32(SCP_BOOT_CFG_ADDR); diff --git a/plat/common/aarch32/plat_common.c b/plat/common/aarch32/plat_common.c index d3799d28..c0238698 100644 --- a/plat/common/aarch32/plat_common.c +++ b/plat/common/aarch32/plat_common.c @@ -1,11 +1,12 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #include <console.h> #include <platform.h> +#include <platform_sp_min.h> #include <xlat_mmu_helpers.h> /* @@ -29,3 +30,14 @@ void sp_min_plat_runtime_setup(void) */ console_uninit(); } + +#if !ERROR_DEPRECATED + +#pragma weak sp_min_early_platform_setup2 + +void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) +{ + sp_min_early_platform_setup((void *) arg0, (void *)arg1); +} +#endif diff --git a/plat/common/aarch64/plat_common.c b/plat/common/aarch64/plat_common.c index cfc0c4f4..080d3569 100644 --- a/plat/common/aarch64/plat_common.c +++ b/plat/common/aarch64/plat_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -20,6 +20,7 @@ #pragma weak bl31_plat_runtime_setup #if !ERROR_DEPRECATED #pragma weak plat_get_syscnt_freq2 +#pragma weak bl31_early_platform_setup2 #endif /* ERROR_DEPRECATED */ #if SDEI_SUPPORT @@ -70,6 +71,12 @@ unsigned int plat_get_syscnt_freq2(void) return (unsigned int)freq; } + +void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) +{ + bl31_early_platform_setup((void *) arg0, (void *)arg1); +} #endif /* ERROR_DEPRECATED */ #if SDEI_SUPPORT diff --git a/plat/common/plat_bl1_common.c b/plat/common/plat_bl1_common.c index b92cf54b..4b1f2334 100644 --- a/plat/common/plat_bl1_common.c +++ b/plat/common/plat_bl1_common.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,8 +7,10 @@ #include <arch_helpers.h> #include <assert.h> #include <bl_common.h> +#include <bl1.h> #include <debug.h> #include <errno.h> +#include <platform.h> #include <platform_def.h> /* @@ -21,6 +23,8 @@ #pragma weak bl1_plat_set_ep_info #pragma weak bl1_plat_get_image_desc #pragma weak bl1_plat_fwu_done +#pragma weak bl1_plat_handle_pre_image_load +#pragma weak bl1_plat_handle_post_image_load unsigned int bl1_plat_get_next_image_id(void) @@ -35,6 +39,11 @@ void bl1_plat_set_ep_info(unsigned int image_id, } +int bl1_plat_handle_pre_image_load(unsigned int image_id) +{ + return 0; +} + /* * Following is the default definition that always * returns BL2 image details. @@ -62,3 +71,54 @@ int bl1_plat_mem_check(uintptr_t mem_base, unsigned int mem_size, assert(0); return -ENOMEM; } + +/* + * Default implementation for bl1_plat_handle_post_image_load(). This function + * populates the default arguments to BL2. The BL2 memory layout structure + * is allocated and the calculated layout is populated in arg1 to BL2. + */ +int bl1_plat_handle_post_image_load(unsigned int image_id) +{ + meminfo_t *bl2_tzram_layout; + meminfo_t *bl1_tzram_layout; + image_desc_t *image_desc; + entry_point_info_t *ep_info; + + if (image_id != BL2_IMAGE_ID) + return 0; + + /* Get the image descriptor */ + image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID); + assert(image_desc != NULL); + + /* Get the entry point info */ + ep_info = &image_desc->ep_info; + + /* Find out how much free trusted ram remains after BL1 load */ + bl1_tzram_layout = bl1_plat_sec_mem_layout(); + + /* + * Create a new layout of memory for BL2 as seen by BL1 i.e. + * tell it the amount of total and free memory available. + * This layout is created at the first free address visible + * to BL2. BL2 will read the memory layout before using its + * memory for other purposes. + */ +#if LOAD_IMAGE_V2 + bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->total_base; +#else + bl2_tzram_layout = (meminfo_t *) bl1_tzram_layout->free_base; +#endif /* LOAD_IMAGE_V2 */ + +#if !ERROR_DEPRECATED + bl1_init_bl2_mem_layout(bl1_tzram_layout, bl2_tzram_layout); +#else + bl1_calc_bl2_mem_layout(bl1_tzram_layout, bl2_tzram_layout); +#endif + + ep_info->args.arg1 = (uintptr_t)bl2_tzram_layout; + + VERBOSE("BL1: BL2 memory layout address = %p\n", + (void *) bl2_tzram_layout); + return 0; +} diff --git a/plat/common/plat_bl2_el3_common.c b/plat/common/plat_bl2_el3_common.c deleted file mode 100644 index 358a02d5..00000000 --- a/plat/common/plat_bl2_el3_common.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <arch_helpers.h> -#include <assert.h> -#include <bl_common.h> -#include <debug.h> -#include <errno.h> -#include <platform_def.h> - -/* - * The following platform functions are weakly defined. They - * are default implementations that allow BL2 to compile in - * absence of real definitions. The Platforms may override - * with more complex definitions. - */ -#pragma weak bl2_el3_plat_prepare_exit - -void bl2_el3_plat_prepare_exit(void) -{ -} diff --git a/plat/common/plat_bl_common.c b/plat/common/plat_bl_common.c new file mode 100644 index 00000000..502bb540 --- /dev/null +++ b/plat/common/plat_bl_common.c @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <arch_helpers.h> +#include <assert.h> +#include <bl_common.h> +#include <debug.h> +#include <errno.h> +#include <platform.h> + +/* + * The following platform functions are weakly defined. The Platforms + * may redefine with strong definition. + */ +#pragma weak bl2_el3_plat_prepare_exit +#pragma weak plat_error_handler +#pragma weak bl2_plat_preload_setup +#pragma weak bl2_plat_handle_pre_image_load +#pragma weak bl2_plat_handle_post_image_load +#pragma weak plat_try_next_boot_source + +void bl2_el3_plat_prepare_exit(void) +{ +} + +void __dead2 plat_error_handler(int err) +{ + while (1) + wfi(); +} + +void bl2_plat_preload_setup(void) +{ +} + +int bl2_plat_handle_pre_image_load(unsigned int image_id) +{ + return 0; +} + +int bl2_plat_handle_post_image_load(unsigned int image_id) +{ + return 0; +} + +int plat_try_next_boot_source(void) +{ + return 0; +} + +#if !ERROR_DEPRECATED +#pragma weak bl2_early_platform_setup2 + +/* + * The following platform API implementation that allow compatibility for + * the older platform APIs. + */ +void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1, + u_register_t arg2, u_register_t arg3) +{ + bl2_early_platform_setup((void *)arg1); +} +#endif diff --git a/plat/common/platform_helpers_default.c b/plat/common/platform_helpers_default.c deleted file mode 100644 index ce1a7317..00000000 --- a/plat/common/platform_helpers_default.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <arch_helpers.h> -#include <platform.h> - -/* - * Placeholder functions which can be redefined by each platfrom. - */ - -#pragma weak plat_error_handler -#pragma weak bl1_plat_handle_pre_image_load -#pragma weak bl1_plat_handle_post_image_load -#pragma weak bl2_plat_preload_setup -#pragma weak bl2_plat_handle_pre_image_load -#pragma weak bl2_plat_handle_post_image_load -#pragma weak plat_try_next_boot_source - -void __dead2 plat_error_handler(int err) -{ - while (1) - wfi(); -} - -int bl1_plat_handle_pre_image_load(void) -{ - return 0; -} - -int bl1_plat_handle_post_image_load(void) -{ - return 0; -} - -void bl2_plat_preload_setup(void) -{ -} - -int bl2_plat_handle_pre_image_load(unsigned int image_id) -{ - return 0; -} - -int bl2_plat_handle_post_image_load(unsigned int image_id) -{ - return 0; -} - -int plat_try_next_boot_source(void) -{ - return 0; -} diff --git a/tools/cert_create/include/tbbr/tbb_ext.h b/tools/cert_create/include/tbbr/tbb_ext.h index 85ad3595..5b427d35 100644 --- a/tools/cert_create/include/tbbr/tbb_ext.h +++ b/tools/cert_create/include/tbbr/tbb_ext.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -13,6 +13,8 @@ enum { TRUSTED_FW_NVCOUNTER_EXT, NON_TRUSTED_FW_NVCOUNTER_EXT, TRUSTED_BOOT_FW_HASH_EXT, + TRUSTED_BOOT_FW_CONFIG_HASH_EXT, + HW_CONFIG_HASH_EXT, TRUSTED_WORLD_PK_EXT, NON_TRUSTED_WORLD_PK_EXT, SCP_FW_CONTENT_CERT_PK_EXT, diff --git a/tools/cert_create/src/tbbr/tbb_cert.c b/tools/cert_create/src/tbbr/tbb_cert.c index c815178c..325b4622 100644 --- a/tools/cert_create/src/tbbr/tbb_cert.c +++ b/tools/cert_create/src/tbbr/tbb_cert.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -26,9 +26,11 @@ static cert_t tbb_certs[] = { .issuer = TRUSTED_BOOT_FW_CERT, .ext = { TRUSTED_FW_NVCOUNTER_EXT, - TRUSTED_BOOT_FW_HASH_EXT + TRUSTED_BOOT_FW_HASH_EXT, + TRUSTED_BOOT_FW_CONFIG_HASH_EXT, + HW_CONFIG_HASH_EXT }, - .num_ext = 2 + .num_ext = 4 }, [TRUSTED_KEY_CERT] = { .id = TRUSTED_KEY_CERT, diff --git a/tools/cert_create/src/tbbr/tbb_ext.c b/tools/cert_create/src/tbbr/tbb_ext.c index 504b0fc0..5f2cec19 100644 --- a/tools/cert_create/src/tbbr/tbb_ext.c +++ b/tools/cert_create/src/tbbr/tbb_ext.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -53,6 +53,26 @@ static ext_t tbb_ext[] = { .asn1_type = V_ASN1_OCTET_STRING, .type = EXT_TYPE_HASH }, + [TRUSTED_BOOT_FW_CONFIG_HASH_EXT] = { + .oid = TRUSTED_BOOT_FW_CONFIG_HASH_OID, + .opt = "tb-fw-config", + .help_msg = "Trusted Boot Firmware Config file", + .sn = "TrustedBootFirmwareConfigHash", + .ln = "Trusted Boot Firmware Config hash", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH, + .optional = 1 + }, + [HW_CONFIG_HASH_EXT] = { + .oid = HW_CONFIG_HASH_OID, + .opt = "hw-config", + .help_msg = "HW Config file", + .sn = "HWConfigHash", + .ln = "HW Config hash", + .asn1_type = V_ASN1_OCTET_STRING, + .type = EXT_TYPE_HASH, + .optional = 1 + }, [TRUSTED_WORLD_PK_EXT] = { .oid = TRUSTED_WORLD_PK_OID, .sn = "TrustedWorldPublicKey", diff --git a/tools/fiptool/tbbr_config.c b/tools/fiptool/tbbr_config.c index 827cab28..2c0adcd2 100644 --- a/tools/fiptool/tbbr_config.c +++ b/tools/fiptool/tbbr_config.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -67,7 +67,17 @@ toc_entry_t toc_entries[] = { .uuid = UUID_NON_TRUSTED_FIRMWARE_BL33, .cmdline_name = "nt-fw" }, - + /* Dynamic Configs */ + { + .name = "HW_CONFIG", + .uuid = UUID_HW_CONFIG, + .cmdline_name = "hw-config" + }, + { + .name = "TB_FW_CONFIG", + .uuid = UUID_TB_FW_CONFIG, + .cmdline_name = "tb-fw-config" + }, /* Key Certificates */ { .name = "Root Of Trust key certificate", |