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-rw-r--r--common/aarch64/early_exceptions.S72
1 files changed, 27 insertions, 45 deletions
diff --git a/common/aarch64/early_exceptions.S b/common/aarch64/early_exceptions.S
index 64bfcd0f..0ef59507 100644
--- a/common/aarch64/early_exceptions.S
+++ b/common/aarch64/early_exceptions.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -31,140 +31,122 @@
#include <asm_macros.S>
#include <bl_common.h>
+/* -----------------------------------------------------------------------------
+ * Very simple stackless exception handlers used by BL2 and BL31 stages.
+ * BL31 uses them before stacks are setup. BL2 uses them throughout.
+ * -----------------------------------------------------------------------------
+ */
.globl early_exceptions
- .section .vectors, "ax"; .align 11
+vector_base early_exceptions
/* -----------------------------------------------------
- * Very simple stackless exception handlers used by BL2
- * and BL31 bootloader stages. BL31 uses them before
- * stacks are setup. BL2 uses them throughout.
- * -----------------------------------------------------
- */
- .align 7
-early_exceptions:
- /* -----------------------------------------------------
- * Current EL with SP0 : 0x0 - 0x180
+ * Current EL with SP0 : 0x0 - 0x200
* -----------------------------------------------------
*/
-SynchronousExceptionSP0:
+vector_entry SynchronousExceptionSP0
mov x0, #SYNC_EXCEPTION_SP_EL0
bl plat_report_exception
b SynchronousExceptionSP0
check_vector_size SynchronousExceptionSP0
- .align 7
-IrqSP0:
+vector_entry IrqSP0
mov x0, #IRQ_SP_EL0
bl plat_report_exception
b IrqSP0
check_vector_size IrqSP0
- .align 7
-FiqSP0:
+vector_entry FiqSP0
mov x0, #FIQ_SP_EL0
bl plat_report_exception
b FiqSP0
check_vector_size FiqSP0
- .align 7
-SErrorSP0:
+vector_entry SErrorSP0
mov x0, #SERROR_SP_EL0
bl plat_report_exception
b SErrorSP0
check_vector_size SErrorSP0
/* -----------------------------------------------------
- * Current EL with SPx: 0x200 - 0x380
+ * Current EL with SPx: 0x200 - 0x400
* -----------------------------------------------------
*/
- .align 7
-SynchronousExceptionSPx:
+vector_entry SynchronousExceptionSPx
mov x0, #SYNC_EXCEPTION_SP_ELX
bl plat_report_exception
b SynchronousExceptionSPx
check_vector_size SynchronousExceptionSPx
- .align 7
-IrqSPx:
+vector_entry IrqSPx
mov x0, #IRQ_SP_ELX
bl plat_report_exception
b IrqSPx
check_vector_size IrqSPx
- .align 7
-FiqSPx:
+vector_entry FiqSPx
mov x0, #FIQ_SP_ELX
bl plat_report_exception
b FiqSPx
check_vector_size FiqSPx
- .align 7
-SErrorSPx:
+vector_entry SErrorSPx
mov x0, #SERROR_SP_ELX
bl plat_report_exception
b SErrorSPx
check_vector_size SErrorSPx
/* -----------------------------------------------------
- * Lower EL using AArch64 : 0x400 - 0x580
+ * Lower EL using AArch64 : 0x400 - 0x600
* -----------------------------------------------------
*/
- .align 7
-SynchronousExceptionA64:
+vector_entry SynchronousExceptionA64
mov x0, #SYNC_EXCEPTION_AARCH64
bl plat_report_exception
b SynchronousExceptionA64
check_vector_size SynchronousExceptionA64
- .align 7
-IrqA64:
+vector_entry IrqA64
mov x0, #IRQ_AARCH64
bl plat_report_exception
b IrqA64
check_vector_size IrqA64
- .align 7
-FiqA64:
+vector_entry FiqA64
mov x0, #FIQ_AARCH64
bl plat_report_exception
b FiqA64
check_vector_size FiqA64
- .align 7
-SErrorA64:
+vector_entry SErrorA64
mov x0, #SERROR_AARCH64
bl plat_report_exception
b SErrorA64
check_vector_size SErrorA64
/* -----------------------------------------------------
- * Lower EL using AArch32 : 0x0 - 0x180
+ * Lower EL using AArch32 : 0x600 - 0x800
* -----------------------------------------------------
*/
- .align 7
-SynchronousExceptionA32:
+vector_entry SynchronousExceptionA32
mov x0, #SYNC_EXCEPTION_AARCH32
bl plat_report_exception
b SynchronousExceptionA32
check_vector_size SynchronousExceptionA32
- .align 7
-IrqA32:
+vector_entry IrqA32
mov x0, #IRQ_AARCH32
bl plat_report_exception
b IrqA32
check_vector_size IrqA32
- .align 7
-FiqA32:
+vector_entry FiqA32
mov x0, #FIQ_AARCH32
bl plat_report_exception
b FiqA32
check_vector_size FiqA32
- .align 7
-SErrorA32:
+vector_entry SErrorA32
mov x0, #SERROR_AARCH32
bl plat_report_exception
b SErrorA32