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2017-06-26Merge pull request #994 from soby-mathew/sm/fwu_fixdavidcunado-arm
Fix FWU and cache helper optimization
2017-06-23Merge pull request #976 from etienne-lms/minor-pscidavidcunado-arm
psci: minor fixes in lib
2017-06-23Merge pull request #997 from dp-arm/dp/spedavidcunado-arm
aarch64: Enable Statistical Profiling Extensions for lower ELs
2017-06-23Fix Tegra CFLAGS usageDouglas Raillard
Use TF_CFLAGS instead of CFLAGS, to allow CFLAGS to be overriden from the make command line. Change-Id: I3e5726c04bcd0176f232581b8be2c94413374ac7 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2017-06-23Merge pull request #995 from davidcunado-arm/dc/init_regdavidcunado-arm
Fully initialise essential control registers
2017-06-23io_dummy: correct sparse warningsEtienne Carriere
Include io_dummy.h header file. Use static for device_type_dummy function. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2017-06-23io_storage: use unsigned int for indexEtienne Carriere
This change avoids warning about type conversion. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2017-06-23PSCI: use same function prototype as in header fileEtienne Carriere
Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2017-06-23delay_timer: correct sparse issues and warningsEtienne Carriere
Use NULL instead of 0 where required. Include headers to have the prototype of the functions. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2017-06-23bl1: include bl1_private.h in aarch* filesEtienne Carriere
This change avoids warnings when setting -Wmissing-prototypes or when using sparse tool. Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2017-06-23context_mgmt: declare extern cm_set_next_context() for AArch32Etienne Carriere
This change avoids warning when setting -Wmissing-prototypes to compile bl1_context_mgmt.c. Reported-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2017-06-23bl: security_state should be of type unsigned intEtienne Carriere
security_state is either 0 or 1. Prevent sign conversion potential error (setting -Werror=sign-conversion results in a build error). Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2017-06-22psci: minor fixes in libEtienne Carriere
Call svc_suspend_finish if registered. psci_get_stat() is static to psci_stat.c Fix types used in comparison. Fix coding style (empty line between variable definition and instructions block). Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2017-06-22Merge pull request #996 from dp-arm/dp/aarch32-813419davidcunado-arm
aarch32: Apply workaround for errata 813419 of Cortex-A57
2017-06-22Apply workarounds for A53 Cat A Errata 835769 and 843419Douglas Raillard
These errata are only applicable to AArch64 state. See the errata notice for more details: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.epm048406/index.html Introduce the build options ERRATA_A53_835769 and ERRATA_A53_843419. Enable both of them for Juno. Apply the 835769 workaround as following: * Compile with -mfix-cortex-a53-835769 * Link with --fix-cortex-a53-835769 Apply the 843419 workaround as following: * Link with --fix-cortex-a53-843419 The erratum 843419 workaround can lead the linker to create new sections suffixed with "*.stub*" and 4KB aligned. The erratum 835769 can lead the linker to create new "*.stub" sections with no particular alignment. Also add support for LDFLAGS_aarch32 and LDFLAGS_aarch64 in Makefile for architecture-specific linker options. Change-Id: Iab3337e338b7a0a16b0d102404d9db98c154f8f8 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2017-06-22aarch32: Apply workaround for errata 813419 of Cortex-A57Dimitris Papastamos
TLBI instructions for monitor mode won't have the desired effect under specific circumstances in Cortex-A57 r0p0. The workaround is to execute DSB and TLBI twice each time. Even though this errata is only needed in r0p0, the current errata framework is not prepared to apply run-time workarounds. The current one is always applied if compiled in, regardless of the CPU or its revision. The `DSB` instruction used when initializing the translation tables has been changed to `DSB ISH` as an optimization and to be consistent with the barriers used for the workaround. NOTE: This workaround is present in AArch64 TF and already enabled by default on Juno. Change-Id: I10b0baa304ed64b13b7b26ea766e61461e759dfa Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-06-22Merge pull request #990 from masahir0y/uniphierdavidcunado-arm
uniphier: embed ROTPK hash into BL1/BL2
2017-06-22Merge pull request #988 from Leo-Yan/fix_cpu_off_v1davidcunado-arm
plat: Hikey960: fix the CPU hotplug
2017-06-22aarch64: Enable Statistical Profiling Extensions for lower ELsdp-arm
SPE is only supported in non-secure state. Accesses to SPE specific registers from SEL1 will trap to EL3. During a world switch, before `TTBR` is modified the SPE profiling buffers are drained. This is to avoid a potential invalid memory access in SEL1. SPE is architecturally specified only for AArch64. Change-Id: I04a96427d9f9d586c331913d815fdc726855f6b0 Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-06-21Fully initialise essential control registersDavid Cunado
This patch updates the el3_arch_init_common macro so that it fully initialises essential control registers rather then relying on hardware to set the reset values. The context management functions are also updated to fully initialise the appropriate control registers when initialising the non-secure and secure context structures and when preparing to leave EL3 for a lower EL. This gives better alignement with the ARM ARM which states that software must initialise RES0 and RES1 fields with 0 / 1. This patch also corrects the following typos: "NASCR definitions" -> "NSACR definitions" Change-Id: Ia8940b8351dc27bc09e2138b011e249655041cfc Signed-off-by: David Cunado <david.cunado@arm.com>
2017-06-21Exit early if size zero for cache helpersSoby Mathew
This patch enables cache helper functions `flush_dcache_range`, `clean_dcache_range` and `invalidate_dcache_range` to exit early if the size argument specified is zero Change-Id: I0b63e8f4bd3d47ec08bf2a0b0b9a7ff8a269a9b0 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-06-21Fix issues in FWU codeSoby Mathew
This patch fixes the following issues in Firmware Update (FWU) code: 1. The FWU layer maintains a list of loaded image ids and while checking for image overlaps, INVALID_IMAGE_IDs were not skipped. The patch now adds code to skip INVALID_IMAGE_IDs. 2. While resetting the state corresponding to an image, the code now resets the memory used by the image only if the image were copied previously via IMAGE_COPY smc. This prevents the invalid zeroing of image memory which are not copied but are directly authenticated via IMAGE_AUTH smc. Change-Id: Idf18e69bcba7259411c88807bd0347d59d9afb8f Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-06-20Merge pull request #983 from dp-arm/dp/aarch32-erratadavidcunado-arm
aarch32: Implement errata workarounds for Cortex A53 and A57
2017-06-20uniphier: embed ROTPK hash into BL1/BL2Masahiro Yamada
Currently, ROTPK_NOT_DEPLOYED flag is set in plat_get_rotpk_info(). It is up to users how to retrieve ROTPK if the ROT verification is desired. This is not nice. This commit improves plat_get_rotpk_info() implementation and automates the ROTPK deployment. UniPhier platform has no ROTPK storage, so it should be embedded in BL1/BL2, like ARM_ROTPK_LOCATION=devel_rsa case. This makes sense because UniPhier platform implements its internal ROM i.e. BL1 is used as updatable pseudo ROM. Things work like this: - ROT_KEY (default: $(BUILD_PLAT)/rot_key.pem) is created if missing. Users can override ROT_KEY from the command line if they want to use a specific ROT key. - ROTPK_HASH is generated based on ROT_KEY. - ROTPK_HASH is included by uniphier_rotpk.S and compiled into BL1/BL2. - ROT_KEY is input to cert_create tool. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-06-20Merge pull request #992 from davidcunado-arm/dc/fix-signed-comparisonsdavidcunado-arm
xlat_tables_v2: fix signed/unsigned comparisons
2017-06-20juno: Fix AArch32 buildDimitris Papastamos
Commit 6de8b24f52cf2bd74adefbaa86dd2a0676c3eaa2 broke Juno AArch32 build. Change-Id: Ied70d9becb86e53ccb46a2e3245e2a551d1bf701 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-06-20aarch32: Fix L2CTRL definition for Cortex A57 and A72Dimitris Papastamos
Fixes ARM-software/tf-issues#495 Change-Id: I6a0aea78f670cc199873218a18af1d9cc2a6fafd Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-06-20aarch32: Implement errata workarounds for Cortex A57Dimitris Papastamos
This brings the implementation on par with the software errata workarounds for AArch64. Change-Id: I98a85fd92e32ae4259f4ec5b3e93cffc87090064 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-06-20aarch32: Implement errata workarounds for Cortex A53Dimitris Papastamos
This brings the implementation on par with the software errata workarounds for AArch64. Change-Id: Id103602e35b1c0ad3705a5b2b7cdb34dd8a8c5e2 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-06-20aarch32: Implement cpu_rev_var_hs()Dimitris Papastamos
Helper function to assist with errata workaround application. Change-Id: Idba42ca238442cc826f43444dbfa754e433a5e5e Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-06-20sp_min: Flush console at end of main()Dimitris Papastamos
Flush the console so the errata report is printed correctly before exit to normal world. Change-Id: Idd6b5199b5fb8bda9d16a7b5c6426cdda7c73167 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-06-20sp_min: Implement `sp_min_plat_runtime_setup()`Dimitris Papastamos
On ARM platforms before exiting from SP_MIN ensure that the default console is switched to the runtime serial port. Change-Id: I0ca0d42cc47e345d56179eac16aa3d6712767c9b Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-06-20xlat_tables_v2: fix signed/unsigned comparisonsVarun Wadekar
This patch changes input param level in xlat_tables_print_internal() to an unsigned int to fix the signed/unsigned comparison warnings. The compiler complains about these warnings, thus halting the build flow for Tegra platforms. Change-Id: Ieccc262a63daca7a26ca6a14d81466397af8b89f Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Signed-off-by: David Cunado <david.cunado@arm.com>
2017-06-20Merge pull request #966 from davidcunado-arm/dc/build_with_gcc6.2davidcunado-arm
Resolve build errors flagged by GCC 6.2
2017-06-20Resolve build errors flagged by GCC 6.2David Cunado
With GCC 6.2 compiler, more C undefined behaviour is being flagged as warnings, which result in build errors in ARM TF build. This patch addresses issue caused by enums with values that exceed maximum value for an int. For these cases the enum is converted to a set of defines. Change-Id: I5114164be10d86d5beef3ea1ed9be5863855144d Signed-off-by: David Cunado <david.cunado@arm.com>
2017-06-20Merge pull request #991 from davidcunado-arm/dc/update_hikeydavidcunado-arm
hikey960: migrate to use A53 specific defines
2017-06-20hikey960: migrate to use A53 specific definesDavid Cunado
The patch fb7d32e5881ef2445e8fe2305005f5590d4a7cfa migrated the CPU libraries to have unique defines, prefixing them with the CPU name. This patch migrates the hikey960 platform port to use the A53 specific defines. Change-Id: Id76f544b0b236bbd4974ab5ffa1203f073c20021 Signed-off-by: David Cunado <david.cunado@arm.com>
2017-06-19plat: Hikey960: fix the CPU hotplugLeo Yan
In CPU off callback function, the old code uses the function hisi_test_pwrdn_allcores() to check if all CPUs in cluster have been powered off and if it's valid then power off the whole cluster. But the function hisi_test_pwrdn_allcores() only maintains the different power states only for CPU suspend/resume flow, so it cannot return correct states for CPU on/off flow. This patch is to change use hisi_test_cpu_down() to check if all CPUs have been powered off, so that can power off the whole cluster properly when all CPUs in cluster have been hotplugged off. Signed-off-by: Tao Wang <kevin.wangtao@hisilicon.com> Signed-off-by: Leo Yan <leo.yan@linaro.org>
2017-06-16Merge pull request #953 from vwadekar/tegra-misra-fixes-v1davidcunado-arm
Tegra misra fixes v1
2017-06-16Merge pull request #984 from masahir0y/uniphierdavidcunado-arm
uniphier memory-overrun bug fix
2017-06-16Merge pull request #986 from jagadeeshujja/jagujj/fix-get-power-statedavidcunado-arm
CSS:Fix scpi "get_power_state" when ARM_PLAT_MT is set
2017-06-15Merge pull request #980 from dp-arm/dp/make-fixdavidcunado-arm
tools: Use exported quiet flag from top-level Makefile
2017-06-15Merge pull request #981 from soby-mathew/sm/cov_scmidavidcunado-arm
Fix coverity error in CSS SCMI driver
2017-06-15Merge pull request #985 from hzhuang1/remove_mailboxdavidcunado-arm
hikey960: remove mailbox driver
2017-06-15CSS:Fix scpi "get_power_state" when ARM_PLAT_MT is setjagadeesh ujja
The ARM_PLAT_MT bit enables the support for MT bit in MPIDR format. This means that the level 0 affinity represents the thread and CPU / Cluster levels are at affinity level 1 and 2 respectively. This was not catered for in the scpi 'css_scp_get_power_state, API. Since the SCPI driver can only cater for single threaded CPUs, this patch fixes the problem by catering for this shift by effectively ignoring the Thread (level 0) affinity level. Change-Id: If44f55c9fb2773c8d3f8a9bbcf5420a6f7409dfe Signed-off-by: jagadeesh ujja <jagadeesh.ujja@arm.com>
2017-06-15hikey960: remove mailbox driverHaojian Zhuang
Since this mailbox driver is abandoned, remove it. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2017-06-15uniphier: fix memory over-run bugMasahiro Yamada
Check the array index before the write. This issue was found by a static analysis tool. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-06-14Tegra186: mce: fix MISRA defectsAnthony Zhou
Main fixes: * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Force operands of an operator to the same type category [Rule 10.4] * Added curly braces ({}) around if/while statements in order to make them compound [Rule 15.6] * Added parentheses [Rule 12.1] * Voided non C-library functions whose return types are not used [Rule 17.7] Change-Id: I91404edec2e2194b1ce2672d2a3fc6a1f5bf41f1 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14Tegra: delay_timer: fix MISRA defectsAnthony Zhou
Main fixes: * Include header file for function declarations [Rule 8.4] * Move global object into function [Rule 8.9] Change-Id: I1bc9f3f0ebd4ffc0b8444ac856cd97b0cb56bda4 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
2017-06-14Tegra: gic: fix MISRA defectsVarun Wadekar
Main fixes: * Use int32_t replace int, use uint32_t replace unsign int [Rule 4.6] * Added explicit casts (e.g. 0U) to integers in order for them to be compatible with whatever operation they're used in [Rule 10.1] * Force operands of an operator to the same type category [Rule 10.4] * Fixed assert/if statements conditions to be essentially boolean [Rule 14.4] * Added curly braces ({}) around if statements in order to make them compound [Rule 15.6] * Convert macros form headers to unsigned ints Change-Id: I8051cc16499cece2039c9751bd347645f40f0901 Signed-off-by: Anthony Zhou <anzhou@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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