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re-enable csu and rdc test for use of the test team
only enable if CSU_RDC_TEST is defined.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
(cherry picked from commit 2eb979f144f1c008f64d4550035ece0ad69a2365)
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Align CSU CSL defines with the rest of the imx8m family
Compile csu and rdc drivers.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
(cherry picked from commit 5e705b7aa02b6f9c969c1febe7fcaed2940ebaca)
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The SCFW commit 3e500fb26979 ("SCF-621: Change pad width in
sc_rm_is_pad_owned() RPC.") changes pad width in sc_rm_is_pad_owned()
RPC, update it accordingly.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
(cherry picked from commit 9b8cf9247f1ba85b520f93cae0bb421feb12e76f)
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update umctl2's setting based on phy training CDD value
to workaround the rank-to-rank space issue.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
(cherry picked from commit 8cd4fa6dfff74b190294141bdc22634a7cb40a30)
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the dfiphymaster setting need to be save/restore to make sure
it aligned with the initial config.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
(cherry picked from commit e9dfde639db8593aa12d779f1990c8bb276e711c)
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the DDR3L & DDR4 can share same piece of code of DVFS, so update
the ddr4 dvfs to support DDR3L too.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
(cherry picked from commit 57bf8a00a74f12671cb38863bbc3606b3834f195)
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the bitfield of active_ranks in MSTR is defined as below.
Correct the rank num get in dram_info.
0x01: one rank;
0x11: two rank;
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
(cherry picked from commit bc9bc03f38fecbf5a2e4d938ed6f45fb3ec0b574)
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In some cases, the bl31 won't be reloaded when spl is not supported,
commit 17de039 adds the save/restore data section to fix boot issues
which is caused by the dirty data in data section of previous boot.
However, sometimes the backup data section in dram won't be erased
totally in board cold reboot, it will be restored and modify the
'correct' data section which will cause the board hang.
This commit uses a global flag 'data_section_restore_flag' which is
initialized as '0x1' and should be stored in data section to indicate
the save/restore behavior.
Test: cold/warm reboot on imx8qm/imx8qxp.
Signed-off-by: Ji Luo <ji.luo@nxp.com>
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The anamix PLL override setting should be cleared after system resume.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
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on list
Only put the necessary power domain that need to on by default in the
init on list
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
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DRAM MMU settings miss the MT_NS on iMX8MM/MN/MP, this breaks the
HAB function since we load image by u-boot in NS mode and authenticate
it in ATF. Without MT_NS, ATF access secure memory which is different
cacheline with non-secure memory.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
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Keep the audiomix power domain always on if the LPA is active &
doing audio playback.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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when LPA is active, system wakeup source still need to be configured
to mask the non-wakeup irq.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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Correct the GPC IMR register offset of MU IRQ mask.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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When system entering DSM mode, the main NOC wrapper only need to
be on if any of the MIX with ADB400 port is on, so update the flow
for this.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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On i.Mx8MQ, the actual system counter freq is 8333333Hz,
have some trailing part, so get the actual freq from the system
counter module register.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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Fix assignment error in CSU_SA() and CSU_HPCTRL().
Change-Id: Ia7210745c4e91e33a1ea825ef2678b2d912a066d
Signed-off-by: Ji Luo <ji.luo@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
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In step12, remove the while loop waiting to align
with the ddr4 dvfs flow on imx_2.0.y.
Tested-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Fix build break for iMX8MQ.
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
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The bit define for ispdwp & ddrmix is wrong in RM, so correct it.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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On i.MX8MP, the SRC GPR9(0x94) is used by memory repair, so choose
SRC GPR10(0x98) as the LPA status sync register. Add use '==' instead
of '&' for LPA active statue check.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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Support stop M7 with SIP call.
Per IC team, to rekick M7 need follow steps.
If M7 already in WFI, perform below steps.
a) Set [0x303A_002C].0=0 [ request SLEEPHOLDREQn ]
b) Wait [0x303A_00EC].1 = 0 [ wait SLEEPHOLDACKn ]
c) Set GPR.CPUWAIT=1
d) Set [0x303A_002C].0=1 [ de-assert SLEEPHOLDREQn ]
e) Set SRC_M7_RCR[3:0] = 0xE0 [ reset M7 core/plat ]
f) Wait SRC_M7_RCR[3:0] = 0x8
g) Init TCM or DDR
h) Set GPR.INITVTOR
i) Set GPR.CPUWAIT=0, M7 starting running
Add a timeout check, if timeout, still perform force reset, in this
way no need to rely on M7 team's image wfi support ready.
Return a1,a2 to caller to check timeout or reset fail.
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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The number of IMRs for each core is 5, so correct
it and replace with a macro.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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The SCFW supports OCRAM retention, so no need to set cpu entry for reboot
to let CPU run from SPL in OCRAM again when reboot, then SPL will reload
images after reboot.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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This part of code is still needed by uboot, so add
it back.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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If the Main NOC is power down before, need to reinit the QoS setting
for A53, GIC & Supermix port.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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The common domain suspend callback function is not suitable
for i.MX8MP due to the wait mode workaround. it will be
removed together with the wait mode workaround in the
future.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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On i.MX8MN & i.MX8MP, the M core enabled check should
relay on the IOMUX GPR CPU_WAIT bit, when this bit is
cleared, it means M core is active & running, so refine
the m4 enabled check method.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Replace the imr offset magic number with macro defines.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Allow OP-TEE to generate a device-tree overlay binary
that will be applied by u-boot on the regular dtb.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Due to the design requirement, the HSIOMIX need to be RPM
always on, so HSIOMIX need to be boot on by default. There
are no way to manage the clocks when doing domain on/off,
add clock handling in TF-A to resolve this issue.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Add the i.MX8MP workaround for wait mode just for Alpha
release, this patch will be dropped in the future.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Add the basic support for i.MX8MP.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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move the gpc reg offset, bit define & macro to a separate header
file for code reuse.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Updating the CPU CORE power up timing to make sure
the RDC reload is done before CPU start to run code
in OCRAM space.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Current reset uses WDOG timeout function and default timeout
value is set to 0.5 second. However, it is better to trigger
reset immediately to speed up reboot process as well as prevent
the scenario of WDOG_B toggling later than CPU reset and PMIC
does NOT reset.
Set the WDE bit when IMX_WDOG_B_RESET is not enabled, or
reboot will fail.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Align code style between 8mq, 8mm and 8mn files.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
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8DX and 8QX share the same die,
so will reuse the same implementation
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
(cherry picked from commit bb209a0b4ccca2aa4a3a887f9606dc4a3d294adf)
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Port and cleanup OP-TEE support.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
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Port and cleanup OP-TEE support.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
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Port and cleanup OP-TEE support.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
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Port and cleanup OP-TEE support.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
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Port and cleanup OP-TEE support.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
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Port and cleanup OP-TEE support.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
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i.MX8 SoC with SCU inside support partition reboot, the partition reboot
will NOT reload the bl31.bin, so the data section could have some dirty
data of previous boot up, it will impact the reboot, so need to restore
the data section for partition reboot.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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i.MX8DXL ONLY supports up to 12*32 interrupt number, so the
first SPI interrupt offset should be from 0x2c.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
(cherry picked from commit cd0519bf70382292768adc1e9c0337808c55f148)
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Add support for new SoC i.MX8DXL
Signed-off-by: Teo Hall <teo.hall@nxp.com>
(cherry picked from a7a008da03cd08cae3387c428ad8145fb1fae354)
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Add trusty support for imx8mq, default load address
and size for trusty os will be 0xfe000000 and 0x2000000.
Signed-off-by: Ji Luo <ji.luo@nxp.com>
(cherry picked from a708794ccde53d8253a74ff578ca9d5258971690)
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Add trusty support for imx8mn, default load address and
size of trusty are 0xbe000000 and 0x2000000.
Signed-off-by: Ji Luo <ji.luo@nxp.com>
(cherry picked from commit 1566947ab431388906d71a1fb48e802fc9a1eec9)
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Add trusty support for imx8mm, default load address
and size of trusty are 0xbe000000 anx 0x2000000.
Signed-off-by: Ji Luo <ji.luo@nxp.com>
(cherry picked from commit 28d3f0fa26ff11efb98281ed603b6f44cea3c6c5)
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