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2018-07-05Fix MISRA Rule 5.1Daniel Boulby
Rule 5.1: External identifiers shall be distinct Some of the identifier names in the GICv3 driver were so long that the first 31 characters were identical. This patch shortens these names to make sure they are different. Fixed for: LOG_LEVEL=50 PLAT=fvp Change-Id: Iecd551e3a015d144716b87b42c83dd3ab8c34d90 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-07-05gicv3: Fix support for systems without secure interruptsAndre Przywara
Accessing the interrupt_props array only happens inside a loop over interrupt_props_num, so the GICv3 driver can cope with no secure interrupts. This allows us to relax the asserts that insists on a non-NULL interrupt_props pointer and at least one secure interrupt. This enables GICv3 platforms which have no need for a secure interrupt. This only covers the non-deprecated code paths. Change-Id: I49db291906512f56af065772f69acb281dfbdcfb Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-06-11drivers: add tzc380 supportPeng Fan
Add tzc380 support. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-03-01Emit warnings when using deprecated GIC initDan Handley
Emit runtime warnings when intializing the GIC drivers using the deprecated method of defining integer interrupt arrays in the GIC driver data structures; interrupt_prop_t arrays should be used instead. This helps platforms detect that they have migration work to do. Previously, no warning was emitted in this case. This affects both the GICv2 and GICv3 drivers. Also use the __deprecated attribute to emit a build time warning if these deprecated fields are used. These warnings are suppressed in the GIC driver compatibility functions but will be visible if platforms use them. Change-Id: I6b6b8f6c3b4920c448b6dcb82fc18442cfdf6c7a Signed-off-by: Dan Handley <dan.handley@arm.com>
2018-03-01Improve MULTI_CONSOLE_API deprecation warningsDan Handley
For platforms that have not migrated to MULTI_CONSOLE_API == 1, there are a lot of confusing deprecated declaration warnings relating to use of console_init() and console_uninit(). Some of these relate to use by the generic code, not the platform code. These functions are not really deprecated but *removed* when MULTI_CONSOLE_API == 1. This patch consolidates these warnings into a single preprocessor warning. The __deprecated attribute is removed from the console_init() and console_uninit() declarations. For preprocessor warnings like this to not cause fatal build errors, this patch adds -Wno-error=cpp to the build flags when ERROR_DEPRECATED == 0. This option (and -Wno-error=deprecated-declarations) is now added to CPPFLAGS instead of TF_CFLAGS to ensure the build flags are used in the assembler as well as the compiler. This patch also disentangles the MULTI_CONSOLE_API and ERROR_DEPRECATED build flags by defaulting MULTI_CONSOLE_API to 0 instead of ERROR_DEPRECATED. This allows platforms that have not migrated to MULTI_CONSOLE_API to use ERROR_DEPRECATED == 1 to emit a more meaningful build error. Finally, this patch bans use of MULTI_CONSOLE_API == 1 and AARCH32, since the AArch32 console implementation does not support MULTI_CONSOLE_API == 1. Change-Id: If762165ddcb90c28aa7a4951aba70cb15c2b709c Signed-off-by: Dan Handley <dan.handley@arm.com>
2018-02-28Fix MISRA rule 8.4 Part 1Roberto Vargas
Rule 8.4: A compatible declaration shall be visible when an object or function with external linkage is defined Fixed for: make DEBUG=1 PLAT=fvp LOG_LEVEL=50 all Change-Id: I7c2ad3f5c015411c202605851240d5347e4cc8c7 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-02-28Fix MISRA rule 8.4 in common codeRoberto Vargas
Rule 8.4: A compatible declaration shall be visible when an object or function with external linkage is defined. Change-Id: I26e042cb251a6f9590afa1340fdac73e42f23979 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-02-28Fix MISRA rule 8.3 in common codeRoberto Vargas
Rule 8.3: All declarations of an object or function shall use the same names and type qualifiers. Change-Id: Iff384187c74a598a4e73f350a1893b60e9d16cec Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-02-26Dynamic cfg: Add HW and TB_FW configs to CoTSoby Mathew
This patch adds image IDs to `hw_config` and `tb_fw_config` and includes them in the default Chain Of Trust (CoT). Change-Id: If7bb3e9be8a5e48be76614b35bf43d58fc7fed12 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2018-02-24Merge pull request #1264 from fengbaopeng/integrationdavidcunado-arm
drivers:ufs: fix hynix ufs bug with quirk on hi36xx SoC
2018-02-24drivers:ufs: fix hynix ufs bug with quirk on hi36xx SoCfengbaopeng
Hynix ufs has deviations on hi36xx platform which will result in ufs bursts transfer failures at a very low probability. To fix the problem, the Hynix device must set the register VS_DebugSaveConfigTime to 0x10, which will set time reference for SaveConfigTime is 250 ns. The time reference for SaveConfigTime is 40 ns by default. Signed-off-by: fengbaopeng <fengbaopeng@hisilicon.com>
2018-02-21Resolve TZC400 build issue when DEBUG=1 and ENABLE_ASSERTIONS=0Soby Mathew
Previously the definition of `_tzc_read_peripheral_id()` was wrapped in ENABLE_ASSERTIONS build flag. This causes build issue for TZC400 driver when DEBUG=1 and ENABLE_ASSERTIONS=0. This patch fixes the same by moving the definitions outside the ENABLE_ASSERTIONS build flag. Change-Id: Ic1cad69f02ce65ac34aefd39eaa96d5781043152 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2018-02-14Remove URLs from commentsAntonio Nino Diaz
This fixes all defects according to MISRA Rule 3.1: "The character sequences /* and // shall not be used within a comment". This affects all URLs in comments, so they have been removed: - The link in `sdei_state.c` can also be found in the documentation file `docs/sdei.rst`. - The bug that the file `io_fip.c` talks about doesn't affect the currently supported version of GCC, so it doesn't make sense to keep the comment. Note that the version of GCC officially supported is the one that comes with Linaro Release 17.10, which is GCC 6.2. - The link in `tzc400.c` was broken, and it didn't correctly direct to the Technical Reference Manual it should. The link has been replaced by the title of the document, which is more convenient when looking for the document. Change-Id: I89f60c25f635fd4c008a5d3a14028f814c147bbe Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-02-01Merge pull request #1236 from dbasehore/gic-save-restoredavidcunado-arm
RK3399 GIC save/restore
2018-01-30Merge pull request #1235 from jwerner-chromium/JW_udelaydavidcunado-arm
Fix udelay issues that can make duration slightly too short
2018-01-25delay_timer: Guarantee that delay time can never be undershotJulius Werner
Delay functions like udelay() are often used to ensure that the necessary time passed to allow some asynchronous event to finish, such as the stabilization delay for a power rail. For these use cases it is not very problematic if the delay is slightly longer than requested, but it is critical that the delay must never be shorter. The current udelay() implementation contains two hazards that may cause the delay to be slightly shorter than intended: Firstly, the amount of ticks to wait is calculated with an integer division, which may cut off the last fraction of ticks needed. Secondly, the delay may be short by a fraction of a tick because we do not know whether the initial ("start") sample of the timer was near the start or near the end of the current tick. Thus, if the code intends to wait for one tick, it might read the timer value close to the end of the current tick and then read it again right after the start of the next tick, concluding that the duration of a full tick has passed when it in fact was just a fraction of it. This patch rounds up the division and always adds one extra tick to counteract both problems and ensure that delays will always be larger but never smaller than requested. Change-Id: Ic5fe5f858b5cdf3c0dbf3e488d4d5702d9569433 Signed-off-by: Julius Werner <jwerner@chromium.org>
2018-01-24Merge pull request #1193 from jwerner-chromium/JW_corebootdavidcunado-arm
New console API and coreboot support [v4]
2018-01-23GICv3: Fix Dist restore for when the GIC is resetDerek Basehore
If the GIC loses power during suspend, which the restore code was written for, exit early in the post restore power sequence. This prevents an assert from tripping, and the power sequence isn't needed in this case anyways. Signed-off-by: Derek Basehore <dbasehore@chromium.org>
2018-01-19Merge pull request #1227 from geesun/qx/emmc_macrosdavidcunado-arm
emmc: add macros CMD21, BUS_WIDTH_DDR_4 and BUS_WIDTH_DDR_8
2018-01-19coreboot: Add support for CBMEM consoleJulius Werner
coreboot supports an in-memory console to store firmware logs even when no serial console is available. It is widely supported by coreboot-compatible bootloaders (including SeaBIOS and GRUB) and can be read by the Linux kernel. This patch allows BL31 to add its own log messages to this console. The driver will be registered automatically if coreboot support is compiled in and detects the presence of a console buffer in the coreboot tables. Change-Id: I31254dfa0c2fdeb7454634134b5707b4b4154907 Signed-off-by: Julius Werner <jwerner@chromium.org>
2018-01-19drivers: cadence: cdns: Update CDNS driver to support MULTI_CONSOLE_APIJulius Werner
This patch updates the Cadence CDNS console driver to support the new console API. The driver will continue to support the old API as well by checking the MULTI_CONSOLE_API compile-time flag. Change-Id: I2ef8fb0d6ab72696997db1e0243a533499569d6b Signed-off-by: Julius Werner <jwerner@chromium.org>
2018-01-19drivers: arm: pl011: Update PL011 driver to support MULTI_CONSOLE_APIJulius Werner
This patch updates the ARM PL011 console driver to support the new console API. The driver will continue to support the old API as well by checking the MULTI_CONSOLE_API compile-time flag. Change-Id: Ic34e4158addbb0c5fae500c9cff899c05a4f4206 Signed-off-by: Julius Werner <jwerner@chromium.org>
2018-01-19drivers: ti: uart: Update 16550 UART driver to support MULTI_CONSOLE_APIJulius Werner
This patch updates the TI 16550 console driver to support the new console API. The driver will continue to support the old API as well by checking the MULTI_CONSOLE_API compile-time flag. Change-Id: I60a44b7ba3c35c74561824c04b8dbe3e3039324c Signed-off-by: Julius Werner <jwerner@chromium.org>
2018-01-19Merge pull request #1200 from robertovargas-arm/bl2-el3davidcunado-arm
Add BL2_AT_EL3 build option
2018-01-18bl2-el3: Don't compile BL1 when BL2_AT_EL3 is defined in FVPRoberto Vargas
This patch modifies the makefiles to avoid the definition of BL1_SOURCES and BL2_SOURCES in the tbbr makefiles, and it lets to the platform makefiles to define them if they actually need these images. In the case of BL2_AT_EL3 BL1 will not be needed usually because the Boot ROM will jump directly to BL2. Change-Id: Ib6845a260633a22a646088629bcd7387fe35dcf9 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-01-17emmc: add macros CMD21, BUS_WIDTH_DDR_4 and BUS_WIDTH_DDR_8Qixiang Xu
Add some macros according to JEDEC Standard Embedded Multi-Media Card (eMMC) Electrical Standard (5.1)": Table 145 - Bus Mode Selection. Change-Id: Iaa45e0582653ef4290efd60d039f0bdc420eeb47 Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
2018-01-11emmc/dw_mmc: fix the assert on HLE bitHaojian Zhuang
When check HLE bit in interrupt register, it should check whether HLE bit is set, not clear. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2017-12-19Merge pull request #1194 from robertovargas-arm/io-fixdavidcunado-arm
io: block: fix block_read/write may read/write overlap buffer
2017-12-13io: block: fix block_read/write may read/write overlap bufferRoberto Vargas
The block operations were trying to optimize the number of memory copies, and it tried to use directly the buffer supplied by the user to them. This was a mistake because it created too many corner cases: 1- It was possible to generate unaligned operations to unaligned buffers. Drivers that were using DMA transfer failed in that case. 2- It was possible to generate read operations with sizes that weren't a multiple of the block size. Some low level drivers assumed that condition and they calculated the number of blocks dividing the number of bytes by the size of the block, without considering the remaining bytes. 3- The block_* operations didn't control the number of bytes actually copied to memory, because the low level drivers were writing directly to the user buffer. This patch rewrite block_read and block_write to use always the device buffer, which the platform ensures that has the correct aligment and the correct size. Change-Id: I5e479bb7bc137e6ec205a8573eb250acd5f40420 Signed-off-by: Qixiang Xu <qixiang.xu@arm.com> Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2017-12-12Add new function-pointer-based console APIJulius Werner
This patch overhauls the console API to allow for multiple console instances of different drivers that are active at the same time. Instead of binding to well-known function names (like console_core_init), consoles now provide a register function (e.g. console_16550_register()) that will hook them into the list of active consoles. All console operations will be dispatched to all consoles currently in the list. The new API will be selected by the build-time option MULTI_CONSOLE_API, which defaults to ${ERROR_DEPRECATED} for now. The old console API code will be retained to stay backwards-compatible to older platforms, but should no longer be used for any newly added platforms and can hopefully be removed at some point in the future. The new console API is intended to be used for both normal (bootup) and crash use cases, freeing platforms of the need to set up the crash console separately. Consoles can be individually configured to be active active at boot (until first handoff to EL2), at runtime (after first handoff to EL2), and/or after a crash. Console drivers should set a sane default upon registration that can be overridden with the console_set_scope() call. Code to hook up the crash reporting mechanism to this framework will be added with a later patch. This patch only affects AArch64, but the new API could easily be ported to AArch32 as well if desired. Change-Id: I35c5aa2cb3f719cfddd15565eb13c7cde4162549 Signed-off-by: Julius Werner <jwerner@chromium.org>
2017-11-23Merge pull request #1145 from etienne-lms/rfc-armv7-2davidcunado-arm
Support ARMv7 architectures
2017-11-21tbbr: Add build flag HASH_ALG to let the user to select the SHAQixiang Xu
The flag support the following values: - sha256 (default) - sha384 - sha512 Change-Id: I7a49d858c361e993949cf6ada0a86575c3291066 Signed-off-by: Qixiang Xu <qixiang.xu@arm.com>
2017-11-13GIC: Fix Group 0 enablingJeenu Viswambharan
At present, the GIC drivers enable Group 0 interrupts only if there are Secure SPIs listed in the interrupt properties/list. This means that, even if there are Group 0 SGIs/PPIs configured, the group remained disabled in the absence of a Group 0 SPI. Modify both GICv2 and GICv3 SGI/PPI configuration to enable Group 0 when corresponding SGIs/PPIs are present. Change-Id: Id123e8aaee0c22b476eebe3800340906d83bbc6d Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-11-13GICv2: Fix populating PE target dataJeenu Viswambharan
This patch brings in the following fixes: - The per-PE target data initialized during power up needs to be flushed so as to be visible to other PEs. - Setup per-PE target data for the primary PE as well. At present, this was only setup for secondary PEs when they were powered on. Change-Id: Ibe3a57c14864e37b2326dd7ab321a5c7bf80e8af Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-11-08ARMv7: GICv2 driver can manage GICv1 with security extensionEtienne Carriere
Some SoCs integrate a GIC in version 1 that is currently not supported by the trusted firmware. This change hijacks GICv2 driver to handle the GICv1 as GICv1 is compatible enough with GICv2 as far as the platform does not attempt to play with virtualization support or some GICv2 specific power features. Note that current trusted firmware does not use these GICv2 features that are not available in GICv1 Security Extension. Change-Id: Ic2cb3055f1319a83455571d6d918661da583f179 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2017-10-16GIC: Allow specifying interrupt propertiesJeenu Viswambharan
The GIC driver initialization currently allows an array of interrupts to be configured as secure. Future use cases would require more interrupt configuration other than just security, such as priority. This patch introduces a new interrupt property array as part of both GICv2 and GICv3 driver data. The platform can populate the array with interrupt numbers and respective properties. The corresponding driver initialization iterates through the array, and applies interrupt configuration as required. This capability, and the current way of supplying array (or arrays, in case of GICv3) of secure interrupts, are however mutually exclusive. Henceforth, the platform should supply either: - A list of interrupts to be mapped as secure (the current way). Platforms that do this will continue working as they were. With this patch, this scheme is deprecated. - A list of interrupt properties (properties include interrupt group). Individual interrupt properties are specified via. descriptors of type 'interrupt_prop_desc_t', which can be populated with the macro INTR_PROP_DESC(). A run time assert checks that the platform doesn't specify both. Henceforth the old scheme of providing list of secure interrupts is deprecated. When built with ERROR_DEPRECATED=1, GIC drivers will require that the interrupt properties are supplied instead of an array of secure interrupts. Add a section to firmware design about configuring secure interrupts. Fixes ARM-software/tf-issues#262 Change-Id: I8eec29e72eb69dbb6bce77879febf32c95376942 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-10-16GIC: Add helpers to set interrupt configurationJeenu Viswambharan
The helpers perform read-modify-write on GIC*_ICFGR registers, but don't serialise callers. Any serialisation must be taken care of by the callers. Change-Id: I71995f82ff2c7f70d37af0ede30d6ee18682fd3f Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-10-16GIC: Add API to set priority maskJeenu Viswambharan
API documentation updated. Change-Id: I40feec1fe67a960d035061b54dd55610bc34ce1d Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-10-16GIC: Add API to set/clear interrupt pendingJeenu Viswambharan
API documentation updated. Change-Id: I14e33cfc7dfa93257c82d76fae186b17a1b6d266 Co-authored-by: Yousuf A <yousuf.sait@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-10-16GIC: Add API to set interrupt routingJeenu Viswambharan
SPIs can be routed to either a specific PE, or to any one of all available PEs. API documentation updated. Change-Id: I28675f634568aaf4ea1aa8aa7ebf25b419a963ed Co-authored-by: Yousuf A <yousuf.sait@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-10-16GIC: Add API to raise secure SGIJeenu Viswambharan
API documentation updated. Change-Id: I129725059299af6cc612bafa8d74817f779d7c4f Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-10-16GIC: Add APIs to set interrupt type and query supportJeenu Viswambharan
The back end GIC driver converts and assigns the interrupt type to suitable group. For GICv2, a build option GICV2_G0_FOR_EL3 is introduced, which determines to which type Group 0 interrupts maps to. - When the build option is set 0 (the default), Group 0 interrupts are meant for Secure EL1. This is presently the case. - Otherwise, Group 0 interrupts are meant for EL3. This means the SPD will have to synchronously hand over the interrupt to Secure EL1. The query API allows the platform to query whether the platform supports interrupts of a given type. API documentation updated. Change-Id: I60fdb4053ffe0bd006b3b20914914ebd311fc858 Co-authored-by: Yousuf A <yousuf.sait@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-10-16GIC: Add API to set interrupt priorityJeenu Viswambharan
API documentation updated. Change-Id: Ib700eb1b8ca65503aeed0ac4ce0e7b934df67ff9 Co-authored-by: Yousuf A <yousuf.sait@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-10-16GIC: Add APIs to enable and disable interruptJeenu Viswambharan
API documentation updated. Change-Id: Ice7511f8df5356851001d2f7dc2a46cfe318f9ba Co-authored-by: Yousuf A <yousuf.sait@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-10-16GIC: Add API to get interrupt active statusJeenu Viswambharan
API documentation updated. Change-Id: I6d61785af0d5330930c709de971a904dc7c3516c Co-authored-by: Yousuf A <yousuf.sait@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-10-16GICv2: Add driver API to set PE target maskJeenu Viswambharan
The PE target mask is used to translate linear PE index (returned by platform core position) to a bit mask used when targeting interrupts to a PE, viz. when raising SGIs and routing SPIs. The platform shall: - Populate the driver data with a pointer to array that's to contain per-PE target masks. - Invoke the new driver API 'gicv2_set_pe_target_mask()' during per-CPU initialization so that the driver populates the target mask for that CPU. Platforms that don't intend to target interrupts or raise SGIs need not populate this. Change-Id: Ic0db54da86915e9dccd82fff51479bc3c1fdc968 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-10-16GIC: Add API to get running priorityJeenu Viswambharan
Document the API in separate platform interrupt controller API document. Change-Id: If18f208e10a8a243f5c59d226fcf48e985941949 Co-authored-by: Yousuf A <yousuf.sait@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-10-06Fix assertion in GIC ITS helperSoby Mathew
This patch fixes an assertion check in the GICv3 ITS helper function. Change-Id: I75f50d7bf6d87c12c6e24a07c9a9889e5facf4a5 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-10-05GICv3: ITS architectural save and restore helpersSoby Mathew
This patch adds functions to save and restore GICv3 ITS registers during system suspend. Please note that the power management of GIC ITS is implementation defined. These functions only implements the architectural part of the ITS power management and they do not restore memory structures or register content required to support ITS. Even if the ITS implementation stores structures in memory, an implementation defined power down sequence is likely to be required to flush some internal ITS caches to memory. If such implementation defined sequence is not followed, the platform must ensure that the ITS is not power gated during system suspend. Change-Id: I5f31e5541975aa7dcaab69b0b7f67583c0e27678 Signed-off-by: Soby Mathew <soby.mathew@arm.com> Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2017-10-05GICv3: add functions for save and restoreSoby Mathew
During system suspend, the GICv3 Distributor and Redistributor context can be lost due to power gating of the system power domain. This means that the GICv3 context needs to be saved prior to system suspend and restored on wakeup. Currently the consensus is that the Firmware should be in charge of this. See tf-issues#464 for more details. This patch introduces helper APIs in the GICv3 driver to save and restore the Distributor and Redistributor contexts. The GICv3 ITS context is not considered in this patch because the specification says that the details of ITS power management is implementation-defined. These APIs are expected to be appropriately invoked by the platform layer during system suspend. Fixes ARM-software/tf-issues#464 Change-Id: Iebb9c6770ab8c4d522546f161fa402d2fe02ec00 Signed-off-by: Soby Mathew <soby.mathew@arm.com> Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
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