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2018-09-28imx8qm/imx8qxp: enable output debug message to SC consoleAnson Huang
Add support for enabling output debug message to SC console, SC_CONSOLE is used to enable/disable it. Example log output on SC console as below: *** Debug Monitor *** >$ NOTICE: smc_fid is c2000003 imx_pwr_domain_on cluster_id 0, cpu_id 1 cluster:0 core:1 is on imx_pwr_domain_on cluster_id 0, cpu_id 2 cluster:0 core:2 is on imx_pwr_domain_on cluster_id 0, cpu_id 3 cluster:0 core:3 is on imx_pwr_domain_on cluster_id 1, cpu_id 0 cluster:1 core:0 is on imx_pwr_domain_on cluster_id 1, cpu_id 1 cluster:1 core:1 is on Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-21Merge pull request #1397 from dp-arm/dp/cortex-a76Dimitris Papastamos
Add support for Cortex-A76 and Cortex-Ares
2018-06-21Merge pull request #1405 from dp-arm/dp/cve_2017_5715Dimitris Papastamos
Fast path SMCCC_ARCH_WORKAROUND_1 calls from AArch32
2018-06-21Merge pull request #1392 from dp-arm/dp/cve_2018_3639Dimitris Papastamos
Implement workaround for CVE-2018-3639 on Cortex A57/A72/A73 and A75 Conflicts: services/arm_arch_svc/arm_arch_svc_setup.c
2018-03-14Fixup `SMCCC_ARCH_FEATURES` semanticsDimitris Papastamos
When querying `SMCCC_ARCH_WORKAROUND_1` through `SMCCC_ARCH_FEATURES`, return either: * -1 to indicate the PE on which `SMCCC_ARCH_FEATURES` is called requires firmware mitigation for CVE-2017-5715 but the mitigation is not compiled in. * 0 to indicate that firmware mitigation is required, or * 1 to indicate that no firmware mitigation is required. This patch complies with v1.2 of the firmware interfaces specification (ARM DEN 0070A). Change-Id: Ibc32d6620efdac6c340758ec502d95554a55f02a Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-03-14Use PFR0 to identify need for mitigation of CVE-2017-5715Dimitris Papastamos
If the CSV2 field reads as 1 then branch targets trained in one context cannot affect speculative execution in a different context. In that case skip the workaround on Cortex A72 and A73. Change-Id: Ide24fb6efc77c548e4296295adc38dca87d042ee Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-02-28Merge pull request #1282 from robertovargas-arm/misra-changesdavidcunado-arm
Misra changes
2018-02-28Fix MISRA rule 8.4 Part 1Roberto Vargas
Rule 8.4: A compatible declaration shall be visible when an object or function with external linkage is defined Fixed for: make DEBUG=1 PLAT=fvp LOG_LEVEL=50 all Change-Id: I7c2ad3f5c015411c202605851240d5347e4cc8c7 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-02-28Fix MISRA rule 8.4 in common codeRoberto Vargas
Rule 8.4: A compatible declaration shall be visible when an object or function with external linkage is defined. Change-Id: I26e042cb251a6f9590afa1340fdac73e42f23979 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-02-28Fix MISRA rule 8.3 in common codeRoberto Vargas
Rule 8.3: All declarations of an object or function shall use the same names and type qualifiers. Change-Id: Iff384187c74a598a4e73f350a1893b60e9d16cec Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-02-28Merge pull request #1287 from davidcunado-arm/dc/fix_misradavidcunado-arm
Update ULL() macro and instances of ull to comply with MISRA
2018-02-28Merge pull request #1286 from antonio-nino-diaz-arm/an/mmu-mismatchdavidcunado-arm
Clarify comments in xlat tables lib and fixes related to the TLB
2018-02-27Merge pull request #1274 from dp-arm/dp/a75davidcunado-arm
AMU fixes for Cortex-A75
2018-02-27Update ULL() macro and instances of ull to comply with MISRADavid Cunado
MISRA C-2012 Rule 7.3 violation: lowercase l shall not be used as literal suffixes. This patch resolves this for the ULL() macro by using ULL suffix instead of the ull suffix. Change-Id: Ia8183c399e74677e676956e8653e82375d0e0a01 Signed-off-by: David Cunado <david.cunado@arm.com>
2018-02-27Invalidate TLB entries during warm bootAntonio Nino Diaz
During the warm boot sequence: 1. The MMU is enabled with the data cache disabled. The MMU table walker is set up to access the translation tables as in cacheable memory, but its accesses are non-cacheable because SCTLR_EL3.C controls them as well. 2. The interconnect is set up and the CPU enters coherency with the rest of the system. 3. The data cache is enabled. If the support for dynamic translation tables is enabled and another CPU makes changes to a region, the changes may only be present in the data cache, not in RAM. The CPU that is booting isn't in coherency with the rest of the system, so the table walker of that CPU isn't either. This means that it may read old entries from RAM and it may have invalid TLB entries corresponding to the dynamic mappings. This is not a problem for the boot code because the mapping is 1:1 and the regions are static. However, the code that runs after the boot sequence may need to access the dynamically mapped regions. This patch invalidates all TLBs during warm boot when the dynamic translation tables support is enabled to prevent this problem. Change-Id: I80264802dc0aa1cb3edd77d0b66b91db6961af3d Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-02-27MISRA fixes for Cortex A75 AMU implementationDimitris Papastamos
Change-Id: I61c9fdfda0c0b3c3ec6249519db23602cf4c2100 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-02-27Refactor AMU support for Cortex A75Dimitris Papastamos
This patch also fixes the assumption that the counters are disabled on the resume path. This is incorrect as the AMU counters are enabled early in the CPU reset function before `cpuamu_context_restore()` runs. Change-Id: I38a94eb166a523f00de18e86860434ffccff2131 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-02-27Factor out CPU AMU helpersDimitris Papastamos
This patch also fixes `cpuamu_write_cpuamcntenclr_el0()` to use an MSR instruction instead of an MRS instruction. Change-Id: Ia6531f64b5ebc60ba432124eaa8d8eaccba40ed0 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-02-27MISRA fixes for AMU/SPE and SVEDimitris Papastamos
Change-Id: I38470528111410cf12b187eb1397d87b812c9416 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-02-27aarch32: Fix multiple bugs in amu_helpers.SDimitris Papastamos
AArch32 uses odd-even pairs when passing 64-bit arguments to functions. For example in `amu_group0_cnt_write_internal()` the second argument is a uint64_t which is passed in r2 and r3. In `amu_group1_set_evtype_internal()` the value that needs to be written to the system register is in r1 not in r0. Change-Id: I20196268fdb1dc9ef6c4ebe61e761fba9623b3f2 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-02-27Assert that group0/group1 counter config is what we expectDimitris Papastamos
Before suspend the AMU counters should be enabled and after resume they should be disabled. Assert that to be consistent with the AArch64 implementation of `amu_context_{save,restore}()`. Change-Id: Ia46f77e4062b93afb93721a2890a9b9d2a7f300e Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-02-27Implement {spe,sve}_supported() helpers and refactor codeDimitris Papastamos
Implement helpers to test if the core supports SPE/SVE. We have a similar helper for AMU and this patch makes all extensions consistent in their implementation. Change-Id: I3e6f7522535ca358259ad142550b19fcb883ca67 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-02-22Fixup AArch32 errata printing frameworkSoby Mathew
The AArch32 assembly implementation of `print_errata_status` did not save a register which was getting clobbered by a `get_cpu_ops_ptr`. This patch fixes that. Change-Id: Id0711e46b7c685a18a10328d4b513e952a5d860b Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2018-02-16Merge pull request #1258 from vchong/optee_dbgdavidcunado-arm
optee: print header info before validate
2018-02-09Merge pull request #1260 from sandrine-bailleux-arm/topics/sb/fix-zlib-builddavidcunado-arm
zlib: Fix build error when LOG_LEVEL=50
2018-02-08zlib: Fix build error when LOG_LEVEL=50Sandrine Bailleux
When enabling VERBOSE() traces, the zlib library fails to compile because of an incompatible format specifier string. Fix that. Change-Id: I74ff1c8dc2e6157ee982f7754bce4504599e3013 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2018-02-08Merge pull request #1254 from masahir0y/bl2-at-el3davidcunado-arm
Fix zero_normalmem() for BL2_AT_EL3
2018-02-08optee: print header info before validateVictor Chong
Currently optee header info is only printed after it is validated, but this does not help with debugging in case of error, so print it before. Signed-off-by: Victor Chong <victor.chong@linaro.org>
2018-02-07Merge pull request #1173 from etienne-lms/armv7-qemudavidcunado-arm
support to boot OP-TEE on AArch32/Armv7+example with Cortex-A15/Qemu
2018-02-06Merge pull request #1224 from masahir0y/gzipdavidcunado-arm
Support GZIP-compressed images for faster loading and verification
2018-02-05aarch32: optee: define the OP-TEE secure payloadEtienne Carriere
AArch32 only platforms can boot the OP-TEE secure firmware as a BL32 secure payload. Such configuration can be defined through AARCH32_SP=optee. The source files can rely on AARCH32_SP_OPTEE to condition OP-TEE boot specific instruction sequences. OP-TEE does not expect ARM Trusted Firmware formatted structure as boot argument. Load sequence is expected to have already loaded to OP-TEE boot arguments into the bl32 entrypoint info structure. Last, AArch32 platform can only boot AArch32 OP-TEE images. Change-Id: Ic28eec5004315fc9111051add6bb1a1d607fc815 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
2018-02-02Merge pull request #1253 from dp-arm/dp/amu32davidcunado-arm
AMUv1 support for AArch32
2018-02-02zlib: add gunzip() supportMasahiro Yamada
This commit adds some more files to use zlib from TF. To use zlib, ->zalloc and ->zfree hooks are needed. The implementation depends on the system. For user-space, the libc provides malloc() and friends. Unfortunately, ARM Trusted Firmware does not provide malloc() or any concept of dynamic memory allocation. I implemented very simple calloc() and free() for this. Stupidly, zfree() never frees memory, but it works enough for this. The purpose of using zlib is to implement gunzip() - this function takes compressed data from in_buf, then dumps the decompressed data to oub_buf. The work_buf is used for memory allocation during the decompress. Upon exit, it updates in_buf and out_buf. If successful, in_buf points to the end of input data, out_buf to the end of the decompressed data. To use this feature, you need to do: - include lib/zlib/zlib.mk from your platform.mk - add $(ZLIB_SOURCES) to your BL*_SOURCES Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-02-02zlib: import zlib files from zlib 1.2.11Masahiro Yamada
Import the following files from zlib 1.2.11: adler32.c crc32.c crc32.h inffast.c inffast.h inffixed.h inflate.c inflate.h inftrees.c inftrees.h zconf.h zlib.h zutil.c zutil.h The original tarball is available from http://zlib.net/ The zlib is free software, distributed under the zlib license. The license text is included in the "zlib.h" file. It should be compatible with BSD-3-Clause. The zlib license is included in the SPDX license list available at https://spdx.org/licenses/, but I did not add the SPDX license tag to the imported files above, to keep them as they are in the upstream project. This seems the general policy for ARM Trusted Firmware, as SPDX License Identifier was not added to files imported from FreeBSD. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-02-01misc_helpers: fix zero_normalmem() for BL2_AT_EL3Masahiro Yamada
The assertion in zero_normalmem() fails for BL2_AT_EL3. This mode is executed in EL3, so it should check sctlr_el3 instead of sctlr_el1. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-01-31AMU: Implement context save/restore for aarch32Joel Hutton
Add amu_context_save() and amu_context_restore() functions for aarch32 Change-Id: I4df83d447adeaa9d9f203e16dc5a919ffc04d87a Signed-off-by: Joel Hutton <joel.hutton@arm.com>
2018-01-31AMU: Add assembler helper functions for aarch32Joel Hutton
Change-Id: Id6dfe885a63561b1d2649521bd020367b96ae1af Signed-off-by: Joel Hutton <joel.hutton@arm.com>
2018-01-29Optimize SMCCC_ARCH_WORKAROUND_1 on Cortex A57/A72/A73 and A75Dimitris Papastamos
This patch implements a fast path for this SMC call on affected PEs by detecting and returning immediately after executing the workaround. NOTE: The MMU disable/enable workaround now assumes that the MMU was enabled on entry to EL3. This is a valid assumption as the code turns on the MMU after reset and leaves it on until the core powers off. Change-Id: I13c336d06a52297620a9760fb2461b4d606a30b3 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-01-29Optimize/cleanup BPIALL workaroundDimitris Papastamos
In the initial implementation of this workaround we used a dedicated workaround context to save/restore state. This patch reduces the footprint as no additional context is needed. Additionally, this patch reduces the memory loads and stores by 20%, reduces the instruction count and exploits static branch prediction to optimize the SMC path. Change-Id: Ia9f6bf06fbf8a9037cfe7f1f1fb32e8aec38ec7d Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-01-29Add support for SMCCC_VERSION in PSCI featuresDimitris Papastamos
On some platforms it may be necessary to discover the SMCCC version via a PSCI features call. Change-Id: I95281ac2263ca9aefda1809eb03464fbdb8ac24d Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-01-25Merge pull request #1228 from dp-arm/dp/cve_2017_5715davidcunado-arm
Workarounds for CVE-2017-5715 on A9/A15 and A17 + serial console reporting
2018-01-24Merge pull request #1193 from jwerner-chromium/JW_corebootdavidcunado-arm
New console API and coreboot support [v4]
2018-01-20Merge pull request #1229 from ↵davidcunado-arm
manojkumar-arm/manojkumar-arm/ca72-aarch32-reset-fix lib/cpus: fix branching in reset function for cortex-a72 AARCH32 mode
2018-01-19coreboot: Add support for CBMEM consoleJulius Werner
coreboot supports an in-memory console to store firmware logs even when no serial console is available. It is widely supported by coreboot-compatible bootloaders (including SeaBIOS and GRUB) and can be read by the Linux kernel. This patch allows BL31 to add its own log messages to this console. The driver will be registered automatically if coreboot support is compiled in and detects the presence of a console buffer in the coreboot tables. Change-Id: I31254dfa0c2fdeb7454634134b5707b4b4154907 Signed-off-by: Julius Werner <jwerner@chromium.org>
2018-01-19Add platform-independent coreboot support libraryJulius Werner
This patch adds the foundation for a platform-independent coreboot support library that can be shared by all platforms that boot BL31 from coreboot (acting as BL2). It adds code to parse the "coreboot table", a data structure that coreboot uses to communicate different kinds of information to later-stage firmware and certain OS drivers. As a first small use case for this information, allow platforms to access the serial console configuration used by coreboot, removing the need to hardcode base address and divisors and allowing Trusted Firmware to benefit from coreboot's user configuration (e.g. which UART to pick and which baud rate to use). Change-Id: I2bfb39cd2609ce6640b844ab68df6c9ae3f28e9e Signed-off-by: Julius Werner <jwerner@chromium.org>
2018-01-19Merge pull request #1200 from robertovargas-arm/bl2-el3davidcunado-arm
Add BL2_AT_EL3 build option
2018-01-19lib/cpus: fix branching in reset function for cortex-a72 AARCH32 modeManoj Kumar
In AARCH32 mode, cortex_a72_reset_func branches to address in lr register instead of r5 register. This leads to linux boot failure of Cortex-A72 cores in AARCH32 mode on Juno-R2 board. This patch fixes the branching of cortex_a72_reset_func to r5 register as in cortex_a57_reset_func implementation. Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
2018-01-18Workaround for CVE-2017-5715 for Cortex A9, A15 and A17Dimitris Papastamos
A per-cpu vbar is installed that implements the workaround by invalidating the branch target buffer (BTB) directly in the case of A9 and A17 and indirectly by invalidating the icache in the case of A15. For Cortex A57 and A72 there is currently no workaround implemented when EL3 is in AArch32 mode so report it as missing. For other vulnerable CPUs (e.g. Cortex A73 and Cortex A75), there are no changes since there is currently no upstream AArch32 EL3 support for these CPUs. Change-Id: Ib42c6ef0b3c9ff2878a9e53839de497ff736258f Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-01-18Print erratum application report for CVE-2017-5715Dimitris Papastamos
Even though the workaround for CVE-2017-5715 is not a CPU erratum, the code is piggybacking on the errata framework to print whether the workaround was applied, missing or not needed. Change-Id: I821197a4b8560c73fd894cd7cd9ecf9503c72fa3 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-01-18Change the default errata format stringDimitris Papastamos
As we are using the errata framework to handle workarounds in a more general sense, change the default string to reflect that. Change-Id: I2e266af2392c9d95e18fe4e965f9a1d46fd0e95e Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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