1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
|
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
#include <assert_macros.S>
#include <cortex_a17.h>
#include <cpu_macros.S>
.macro assert_cache_enabled
#if ENABLE_ASSERTIONS
ldcopr r0, SCTLR
tst r0, #SCTLR_C_BIT
ASM_ASSERT(eq)
#endif
.endm
func cortex_a17_disable_smp
ldcopr r0, ACTLR
bic r0, #CORTEX_A17_ACTLR_SMP_BIT
stcopr r0, ACTLR
isb
dsb sy
bx lr
endfunc cortex_a17_disable_smp
func cortex_a17_enable_smp
ldcopr r0, ACTLR
orr r0, #CORTEX_A17_ACTLR_SMP_BIT
stcopr r0, ACTLR
isb
bx lr
endfunc cortex_a17_enable_smp
func cortex_a17_reset_func
b cortex_a17_enable_smp
endfunc cortex_a17_reset_func
func cortex_a17_core_pwr_dwn
push {r12, lr}
assert_cache_enabled
/* Flush L1 cache */
mov r0, #DC_OP_CISW
bl dcsw_op_level1
/* Exit cluster coherency */
pop {r12, lr}
b cortex_a17_disable_smp
endfunc cortex_a17_core_pwr_dwn
func cortex_a17_cluster_pwr_dwn
push {r12, lr}
assert_cache_enabled
/* Flush L1 caches */
mov r0, #DC_OP_CISW
bl dcsw_op_level1
bl plat_disable_acp
/* Exit cluster coherency */
pop {r12, lr}
b cortex_a17_disable_smp
endfunc cortex_a17_cluster_pwr_dwn
declare_cpu_ops cortex_a17, CORTEX_A17_MIDR, \
cortex_a17_reset_func, \
cortex_a17_core_pwr_dwn, \
cortex_a17_cluster_pwr_dwn
|
