imx6qdl.dtsi: add additional pin groups

Add groups required by colibri-imx6

1 files changed, 111 insertions, 28 deletions

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 87cd94d70ad2..7a67952e73cc 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1069,6 +1069,7 @@
 				MX6QDL_PAD_DISP0_DAT19__AUD5_RXD  0x130b0
 			>;
 		};
+
 		pinctrl_audmux_4: audmux-4 {
 			fsl,pins = <
 				MX6QDL_PAD_DISP0_DAT20__AUD4_TXC  0x130b0
@@ -1077,6 +1078,15 @@
 				MX6QDL_PAD_DISP0_DAT23__AUD4_RXD  0x130b0
 			>;
 		};
+
+		pinctrl_audmux_5: audmux-5 {
+			fsl,pins = <
+				MX6QDL_PAD_KEY_COL0__AUD5_TXC  0x130b0
+				MX6QDL_PAD_KEY_ROW0__AUD5_TXD  0x130b0
+				MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
+				MX6QDL_PAD_KEY_ROW1__AUD5_RXD  0x130b0
+			>;
+		};
 	};
 
 	ecspi1 {
@@ -1130,6 +1140,16 @@
 		};
 	};
 
+	ecspi4 {
+		pinctrl_ecspi4_1: ecspi4grp-1 {
+			fsl,pins = <
+				MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
+				MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
+				MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
+			>;
+		};
+	};
+
 	enet {
 		pinctrl_enet_1: enetgrp-1 {
 			fsl,pins = <
@@ -1214,6 +1234,20 @@
 			>;
 		};
 
+		/* RMII */
+		pinctrl_enet_5: enetgrp-5 {
+			fsl,pins = <
+				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
+				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
+				MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0	0x1b0b0
+				MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1	0x1b0b0
+				MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER	0x1b0b0
+				MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x1b0b0
+				MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0	0x1b0b0
+				MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1	0x1b0b0
+				MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN	0x1b0b0
+			>;
+		};
 	};
 
 	esai {
@@ -1519,34 +1553,61 @@
 
 		pinctrl_ipu1_5: ipu1grp-5 {
 			fsl,pins = <
-                                MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK	0x61
-                                MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15	0x61               /* DE */
-                                MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02	0x61                /* HSync */
-                                MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03	0x61                /* VSync */
-                                MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00	0x61
-                                MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01	0x61
-                                MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02	0x61
-                                MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03	0x61
-                                MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04	0x61
-                                MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05	0x61
-                                MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06	0x61
-                                MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07	0x61
-                                MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08	0x61
-                                MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09	0x61
-                                MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10	0x61
-                                MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11	0x61
-                                MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12	0x61
-                                MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13	0x61
-                                MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14	0x61
-                                MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15	0x61
-                                MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16	0x61
-                                MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17	0x61
-                                MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18	0x61
-                                MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19	0x61
-                                MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20	0x61
-                                MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21	0x61
-                                MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22	0x61
-                                MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23	0x61
+				MX6QDL_PAD_EIM_A16__IPU1_DI1_DISP_CLK	0x61
+				MX6QDL_PAD_EIM_DA10__IPU1_DI1_PIN15	0x61                /* DE */
+				MX6QDL_PAD_EIM_DA11__IPU1_DI1_PIN02	0x61                /* HSync */
+				MX6QDL_PAD_EIM_DA12__IPU1_DI1_PIN03	0x61                /* VSync */
+				MX6QDL_PAD_EIM_DA9__IPU1_DISP1_DATA00	0x61
+				MX6QDL_PAD_EIM_DA8__IPU1_DISP1_DATA01	0x61
+				MX6QDL_PAD_EIM_DA7__IPU1_DISP1_DATA02	0x61
+				MX6QDL_PAD_EIM_DA6__IPU1_DISP1_DATA03	0x61
+				MX6QDL_PAD_EIM_DA5__IPU1_DISP1_DATA04	0x61
+				MX6QDL_PAD_EIM_DA4__IPU1_DISP1_DATA05	0x61
+				MX6QDL_PAD_EIM_DA3__IPU1_DISP1_DATA06	0x61
+				MX6QDL_PAD_EIM_DA2__IPU1_DISP1_DATA07	0x61
+				MX6QDL_PAD_EIM_DA1__IPU1_DISP1_DATA08	0x61
+				MX6QDL_PAD_EIM_DA0__IPU1_DISP1_DATA09	0x61
+				MX6QDL_PAD_EIM_EB1__IPU1_DISP1_DATA10	0x61
+				MX6QDL_PAD_EIM_EB0__IPU1_DISP1_DATA11	0x61
+				MX6QDL_PAD_EIM_A17__IPU1_DISP1_DATA12	0x61
+				MX6QDL_PAD_EIM_A18__IPU1_DISP1_DATA13	0x61
+				MX6QDL_PAD_EIM_A19__IPU1_DISP1_DATA14	0x61
+				MX6QDL_PAD_EIM_A20__IPU1_DISP1_DATA15	0x61
+				MX6QDL_PAD_EIM_A21__IPU1_DISP1_DATA16	0x61
+				MX6QDL_PAD_EIM_A22__IPU1_DISP1_DATA17	0x61
+				MX6QDL_PAD_EIM_A23__IPU1_DISP1_DATA18	0x61
+				MX6QDL_PAD_EIM_A24__IPU1_DISP1_DATA19	0x61
+				MX6QDL_PAD_EIM_D31__IPU1_DISP1_DATA20	0x61
+				MX6QDL_PAD_EIM_D30__IPU1_DISP1_DATA21	0x61
+				MX6QDL_PAD_EIM_D26__IPU1_DISP1_DATA22	0x61
+				MX6QDL_PAD_EIM_D27__IPU1_DISP1_DATA23	0x61
+			>;
+		};
+
+		pinctrl_ipu1_6: ipu1grp-6 {
+			fsl,pins = <
+				MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
+				MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15       0x10
+				MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02        0x10
+				MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03        0x10
+				MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00   0x10
+				MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01   0x10
+				MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02   0x10
+				MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03   0x10
+				MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04   0x10
+				MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05   0x10
+				MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06   0x10
+				MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07   0x10
+				MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08   0x10
+				MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09   0x10
+				MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10  0x10
+				MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11  0x10
+				MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12  0x10
+				MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13  0x10
+				MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14  0x10
+				MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15  0x10
+				MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16  0x10
+				MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17  0x10
 			>;
 		};
 	};
@@ -1644,6 +1705,12 @@
 				MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
 			>;
 		};
+
+		pinctrl_spdif_3: spdifgrp-3 {
+			fsl,pins = <
+				MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
+			>;
+		};
 	};
 
 	uart1 {
@@ -1669,6 +1736,14 @@
 				MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x1b0b1
 			>;
 		};
+
+		pinctrl_uart1_4: uart1grp-4 { /* Additional DTR, DSR, DCD */
+			fsl,pins = <
+				MX6QDL_PAD_EIM_D23__UART1_DCD_B 0x1b0b0
+				MX6QDL_PAD_EIM_D24__UART1_DTR_B 0x1b0b0
+				MX6QDL_PAD_EIM_D25__UART1_DSR_B 0x1b0b0
+			>;
+		};
 	};
 
 	uart2 {
@@ -1723,6 +1798,7 @@
 				MX6QDL_PAD_EIM_EB3__UART3_RTS_B   0x1b0b1
 			>;
 		};
+
 		pinctrl_uart3_2: uart3grp-2 {
 			fsl,pins = <
 				MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
@@ -1731,6 +1807,13 @@
 				MX6QDL_PAD_EIM_D31__UART3_RTS_B   0x1b0b1
 			>;
 		};
+
+		pinctrl_uart3_3: uart3grp-3 {
+			fsl,pins = <
+				MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
+				MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
+			>;
+		};
 	};
 
 	uart4 {