ENGR00316182: [imx6x] Fix bugs in clock and cpufreq code.

Cpufreq code:
1. Busfreq can be dropped to 24MH only when CPU freq is at the lowest setpoint (396MHz). The
code was incorrectly releasing the request for high busfreq even when cpufreq was at 792MHz.
This caused incorrect pll2 behavior as the busfreq code expects CPUFREQ to be at 396MHz and
to be sourced from PLL2_PFD2_396M when the switch to low_bus_freq is requested.

Clock code:
1. Ensure osc_clk usecount is also updated when pll2 or pll1 usecount is changed.
This fixes a debug warning message when CLK_DEBUG is enabled.

Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
(cherry picked from commit d08a8a2ed28d9ea42dff9ff82a115072f84630a9)

2 files changed, 11 insertions, 4 deletions

diff --git a/arch/arm/mach-mx6/clock_mx6sl.c b/arch/arm/mach-mx6/clock_mx6sl.c
index 91edafd5c37e..4b5b3f1082f5 100755
--- a/arch/arm/mach-mx6/clock_mx6sl.c
+++ b/arch/arm/mach-mx6/clock_mx6sl.c
@@ -1187,8 +1187,10 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
 		if (pll1_sw_clk.parent != &pll2_pfd2_400M) {
 			if (pll2_pfd2_400M.usecount == 0) {
 				/* Check if PLL2 needs to be enabled also. */
-				if (pll2_528_bus_main_clk.usecount == 0)
+				if (pll2_528_bus_main_clk.usecount == 0) {
 					pll2_528_bus_main_clk.enable(&pll2_528_bus_main_clk);
+					osc_clk.usecount++;
+				}
 				/* Ensure parent usecount is
 				  * also incremented.
 				  */
@@ -1205,6 +1207,7 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
 		if (!pll1_enabled) {
 			pll1_sys_main_clk.enable(&pll1_sys_main_clk);
 			pll1_sys_main_clk.usecount = 1;
+			osc_clk.usecount++;
 		}
 		if (cpu_op_tbl[i].pll_rate != clk_get_rate(&pll1_sys_main_clk)) {
 			if (pll1_sw_clk.parent == &pll1_sys_main_clk) {
@@ -1227,8 +1230,10 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
 				  * also decremented.
 				  */
 				pll2_528_bus_main_clk.usecount--;
-				if (pll2_528_bus_main_clk.usecount == 0)
+				if (pll2_528_bus_main_clk.usecount == 0) {
 					pll2_528_bus_main_clk.disable(&pll2_528_bus_main_clk);
+					osc_clk.usecount--;
+				}
 			}
 		}
 		arm_needs_pll2_400 = false;
@@ -1267,6 +1272,7 @@ static int _clk_arm_set_rate(struct clk *clk, unsigned long rate)
 	if (pll1_sys_main_clk.usecount == 1 && arm_needs_pll2_400) {
 		pll1_sys_main_clk.disable(&pll1_sys_main_clk);
 		pll1_sys_main_clk.usecount = 0;
+		osc_clk.usecount--;
 	}
 
 	spin_unlock_irqrestore(&mx6sl_clk_lock, flags);
diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c
index 47a70d96b24c..1be2957c3a85 100755
--- a/arch/arm/plat-mxc/cpufreq.c
+++ b/arch/arm/plat-mxc/cpufreq.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010-2013 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2010-2014 Freescale Semiconductor, Inc. All Rights Reserved.
  */
 
 /*
@@ -147,7 +147,8 @@ int set_cpu_freq(int freq)
 			}
 		}
 		/* Check if the bus freq can be decreased.*/
-		bus_freq_update(cpu_clk, false);
+		if (freq == cpu_op_tbl[cpu_op_nr - 1].cpu_rate)
+			bus_freq_update(cpu_clk, false);
 	}
 
 	return ret;