diff options
| author | Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com> | 2014-06-26 16:45:50 -0500 |
|---|---|---|
| committer | Peng Fushi <fushi.peng@freescale.com> | 2014-08-28 15:29:46 +0800 |
| commit | 584028a9549f008937d72dadfcfac9a000c38190 (patch) | |
| tree | cf56d8ac2e55731935626729c82dee9aad1ded89 | |
| parent | 6c66a065ee446e5ef4a6939f7ac1386143f9905f (diff) | |
ENGR00320182 [iMX6DQ/iMX6DL] Fix bug in DLL off mode code in DDR3 frequency change procedure
A missing end of comment inadvertently ensured that the DLL off
procedure was executed even when the DLL was already disabled (switching
from 24MHz to 50MHz and vice-versa).
This patch fixes the above issue. And also ensures that automatic entry into
self-refresh is enabled for both DLL ON and DLL OFF modes.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
| -rw-r--r-- | arch/arm/mach-mx6/mx6_ddr_freq.S | 21 |
1 files changed, 7 insertions, 14 deletions
diff --git a/arch/arm/mach-mx6/mx6_ddr_freq.S b/arch/arm/mach-mx6/mx6_ddr_freq.S index 6061fbbd7619..c97a082fd83f 100644 --- a/arch/arm/mach-mx6/mx6_ddr_freq.S +++ b/arch/arm/mach-mx6/mx6_ddr_freq.S @@ -583,7 +583,7 @@ poll_dvfs_clear_1: cmp r0, #0x2000000 beq poll_dvfs_clear_1 - /* if DLL was previously on, continue DLL off routine + /* if DLL was previously on, continue DLL off routine */ cmp r9, #1 beq continue_dll_off_3 @@ -692,12 +692,6 @@ update_iomux: orr r0, r0, #0x20000000 str r0, [r5, r2] - /* MMDC0_MAPSR adopt power down enable */ - /* setmem /32 0x021b0404 = 0x00011006 */ - ldr r0, [r5, #0x404] - bic r0, r0, #0x01 - str r0, [r5, #0x404] - /* frc_msr + mu bypass*/ ldr r0, =0x00000060 str r0, [r5, #0x8b8] @@ -976,12 +970,6 @@ cont15: cmp r1, #0 bgt delay15 - /* MMDC0_MAPSR adopt power down enable */ - /* setmem /32 0x021b0404 = 0x00011006 */ - ldr r0, [r5, #0x404] - bic r0, r0, #0x01 - str r0, [r5, #0x404] - /* Enable MMDC power down timer. */ ldr r0, [r5, #0x4] orr r0, r0, #0x5500 @@ -1029,6 +1017,11 @@ poll_conreq_clear_2: beq poll_conreq_clear_2 done: + /* MMDC0_MAPSR adopt power down enable */ + ldr r0, [r5, #0x404] + bic r0, r0, #0x01 + str r0, [r5, #0x404] + #ifdef CONFIG_CACHE_L2X0 /* Enable L2. */ ldr r1, =L2_BASE_ADDR @@ -1068,8 +1061,8 @@ done: /* Flush the Branch Target Address Cache (BTAC) */ ldr r6, =0x0 mcr p15, 0, r6, c7, c1, 6 - /* Restore registers */ + /* Restore registers */ ldmfd sp!, {r4 - r11} mov pc, lr |