diff options
| author | Antti P Miettinen <amiettinen@nvidia.com> | 2011-10-11 12:01:42 +0300 |
|---|---|---|
| committer | Varun Colbert <vcolbert@nvidia.com> | 2011-10-13 12:58:44 -0700 |
| commit | ff32585e71fdb9b66180d6f1940736c505aaf51c (patch) | |
| tree | bb29bdfd71fea27e256cbd4c103f81861129beae | |
| parent | 207cfee73aea429881341c29c71d7514eaf56505 (diff) | |
ARM: mm: cache-l2x0: Fix L2X0_AUX_CTRL_WAY_SIZE_MASK
The Auxiliary Control Register for Way-size is three bits.
Mask should be 7.
Change-Id: I2fce4596a2b8ce46b3072005ff44379804bbb3e7
Reviewed-on: http://git-master/r/57256
Reviewed-by: Antti Miettinen <amiettinen@nvidia.com>
Tested-by: Antti Miettinen <amiettinen@nvidia.com>
Reviewed-by: Hiroshi Doyu <hdoyu@nvidia.com>
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
| -rw-r--r-- | arch/arm/include/asm/hardware/cache-l2x0.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h index 8fd87fe339d1..5a27c1954389 100644 --- a/arch/arm/include/asm/hardware/cache-l2x0.h +++ b/arch/arm/include/asm/hardware/cache-l2x0.h @@ -64,7 +64,7 @@ #define L2X0_AUX_CTRL_MASK 0xc0000fff #define L2X0_AUX_CTRL_ASSOCIATIVITY_SHIFT 16 #define L2X0_AUX_CTRL_WAY_SIZE_SHIFT 17 -#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x3 << 17) +#define L2X0_AUX_CTRL_WAY_SIZE_MASK (0x7 << 17) #define L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT 22 #define L2X0_AUX_CTRL_NS_LOCKDOWN_SHIFT 26 #define L2X0_AUX_CTRL_NS_INT_CTRL_SHIFT 27 |