diff options
| author | Haojian Zhuang <haojian.zhuang@linaro.org> | 2014-04-02 21:31:50 +0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2014-08-07 14:52:36 -0700 |
| commit | 8702256f25b7a6955fcb94c4f2901b7410f080ee (patch) | |
| tree | df5a4609fe34c7008d596396dcd6cca29dade025 | |
| parent | 4427d35e84912a43eac2605fe4e0425d892998d7 (diff) | |
ARM: dts: fix L2 address in Hi3620
commit 28c9770bcbd2b6dbab99669825a2f8fa69e6d35b upstream.
Fix the address of L2 controler register in hi3620 SoC.
This has been wrong from the point that the file was merged
in v3.14.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Acked-by: Wei Xu <xuwei5@hisilicon.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| -rw-r--r-- | arch/arm/boot/dts/hi3620.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/hi3620.dtsi b/arch/arm/boot/dts/hi3620.dtsi index ab1116d086be..83a5b8685bd9 100644 --- a/arch/arm/boot/dts/hi3620.dtsi +++ b/arch/arm/boot/dts/hi3620.dtsi @@ -73,7 +73,7 @@ L2: l2-cache { compatible = "arm,pl310-cache"; - reg = <0xfc10000 0x100000>; + reg = <0x100000 0x100000>; interrupts = <0 15 4>; cache-unified; cache-level = <2>; |