diff options
| author | Huacai Chen <chenhc@lemote.com> | 2017-03-16 21:00:28 +0800 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2017-05-25 15:44:47 +0200 |
| commit | 07d8aabff4903065bb472df9b040b8688fdc75a2 (patch) | |
| tree | fd1ba490fe0285acac36bdcf295d2ce4580ec798 | |
| parent | 6d6a43a086117930b5acd79c9350e00ef56027fa (diff) | |
MIPS: Loongson-3: Select MIPS_L1_CACHE_SHIFT_6
commit 17c99d9421695a0e0de18bf1e7091d859e20ec1d upstream.
Some newer Loongson-3 have 64 bytes cache lines, so select
MIPS_L1_CACHE_SHIFT_6.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J . Hill <Steven.Hill@caviumnetworks.com>
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/15755/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| -rw-r--r-- | arch/mips/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 5a4f2eb9d0d5..5e844f68e847 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1368,6 +1368,7 @@ config CPU_LOONGSON3 select WEAK_ORDERING select WEAK_REORDERING_BEYOND_LLSC select MIPS_PGD_C0_CONTEXT + select MIPS_L1_CACHE_SHIFT_6 select GPIOLIB help The Loongson 3 processor implements the MIPS64R2 instruction |