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authorPantelis Antoniou <pantelis.antoniou@konsulko.com>2015-05-13 11:04:34 +0300
committerTony Lindgren <tony@atomide.com>2015-05-20 11:21:50 -0700
commit5d1a2961adf906f965b00eb8059fd2e0585e0e09 (patch)
treedb556bb1ed7ef7f4e8b3e3fb53724d04322ca860 /arch/arm/boot/dts/am335x-bone-common.dtsi
parent3aa59200f8d24a533c5b6e1f46d2d8ff205b0207 (diff)
ARM: dts: Beaglebone i2c definitions
The beaglebone family of boards contain two I2C busses enabled. The first one with a baseboard identification EEPROM and a cape I2C bus. Signed-off-by: Pantelis Antoniou <pantelis.antoniou@konsulko.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/am335x-bone-common.dtsi')
-rw-r--r--arch/arm/boot/dts/am335x-bone-common.dtsi66
1 files changed, 66 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
index c3255e0c90aa..236b7db789b0 100644
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -81,6 +81,13 @@
>;
};
+ i2c2_pins: pinmux_i2c2_pins {
+ pinctrl-single,pins = <
+ 0x178 (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_ctsn.i2c2_sda */
+ 0x17c (PIN_INPUT_PULLUP | MUX_MODE3) /* uart1_rtsn.i2c2_scl */
+ >;
+ };
+
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
@@ -218,8 +225,67 @@
reg = <0x24>;
};
+ baseboard_eeprom: baseboard_eeprom@50 {
+ compatible = "at,24c256";
+ reg = <0x50>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ baseboard_data: baseboard_data@0 {
+ reg = <0 0x100>;
+ };
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2_pins>;
+
+ status = "okay";
+ clock-frequency = <100000>;
+
+ cape_eeprom0: cape_eeprom0@54 {
+ compatible = "at,24c256";
+ reg = <0x54>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cape0_data: cape_data@0 {
+ reg = <0 0x100>;
+ };
+ };
+
+ cape_eeprom1: cape_eeprom1@55 {
+ compatible = "at,24c256";
+ reg = <0x55>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cape1_data: cape_data@0 {
+ reg = <0 0x100>;
+ };
+ };
+
+ cape_eeprom2: cape_eeprom2@56 {
+ compatible = "at,24c256";
+ reg = <0x56>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cape2_data: cape_data@0 {
+ reg = <0 0x100>;
+ };
+ };
+
+ cape_eeprom3: cape_eeprom3@57 {
+ compatible = "at,24c256";
+ reg = <0x57>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ cape3_data: cape_data@0 {
+ reg = <0 0x100>;
+ };
+ };
};
+
/include/ "tps65217.dtsi"
&tps {