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authorJoel Stanley <joel@jms.id.au>2019-09-11 17:56:13 +0100
committerArnd Bergmann <arnd@arndb.de>2019-09-12 12:05:08 +0200
commit2ca5646b5c2fdb3806c48f03c77859601e78edb7 (patch)
tree5f036a2b284f3b23699aa9f195e126e7209ad683 /arch/arm/boot/dts/aspeed-ast2600-evb.dts
parent4e53a92cdd1297b6a9b9712004de51936f986914 (diff)
ARM: dts: aspeed: Add AST2600 and EVB
The AST2600 is a new SoC by ASPEED. It contains a dual core Cortex A7 CPU and shares many periperhals with the existing AST2400 and AST2500. Link: https://lore.kernel.org/r/20190911165614.31641-1-joel@jms.id.au Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/boot/dts/aspeed-ast2600-evb.dts')
-rw-r--r--arch/arm/boot/dts/aspeed-ast2600-evb.dts80
1 files changed, 80 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
new file mode 100644
index 000000000000..9870553919b7
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright 2019 IBM Corp.
+
+/dts-v1/;
+
+#include "aspeed-g6.dtsi"
+
+/ {
+ model = "AST2600 EVB";
+ compatible = "aspeed,ast2600";
+
+ aliases {
+ serial4 = &uart5;
+ };
+
+ chosen {
+ bootargs = "console=ttyS4,115200n8";
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x80000000 0x80000000>;
+ };
+};
+
+&mdio1 {
+ status = "okay";
+
+ ethphy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+};
+
+&mdio2 {
+ status = "okay";
+
+ ethphy2: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+};
+
+&mdio3 {
+ status = "okay";
+
+ ethphy3: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+};
+
+&mac1 {
+ status = "okay";
+
+ phy-mode = "rgmii";
+ phy-handle = <&ethphy1>;
+};
+
+&mac2 {
+ status = "okay";
+
+ phy-mode = "rgmii";
+ phy-handle = <&ethphy2>;
+};
+
+&mac3 {
+ status = "okay";
+
+ phy-mode = "rgmii";
+ phy-handle = <&ethphy3>;
+};
+
+&emmc {
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};