diff options
| author | Joel Stanley <joel@jms.id.au> | 2018-02-19 18:05:40 +1030 |
|---|---|---|
| committer | Joel Stanley <joel@jms.id.au> | 2018-02-21 14:53:28 +1030 |
| commit | fd2de0a7317875fecec18b6755b1b171f17490c0 (patch) | |
| tree | c730cd0b3bc74b90f52fec65781c211dbd6b6ccc /arch/arm/boot/dts/aspeed-g4.dtsi | |
| parent | f4c37354565d347575254d3775ae1aaccb05dbbe (diff) | |
ARM: dts: aspeed: Add LPC reset controller node
On both the ast2400 and ast2500 SoCs, the LPC reset controller is
required to bring the UARTs out of reset without waiting for the LPC
reset to be deasserted.
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Diffstat (limited to 'arch/arm/boot/dts/aspeed-g4.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/aspeed-g4.dtsi | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi index 48c28a71ae7e..36ae23aa3b48 100644 --- a/arch/arm/boot/dts/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed-g4.dtsi @@ -162,6 +162,7 @@ reg-shift = <2>; interrupts = <9>; clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>; + resets = <&lpc_reset 4>; no-loopback-test; status = "disabled"; }; @@ -249,6 +250,12 @@ reg = <0x20 0x24 0x48 0x8>; }; + lpc_reset: reset-controller@18 { + compatible = "aspeed,ast2400-lpc-reset"; + reg = <0x18 0x4>; + #reset-cells = <1>; + }; + ibt: ibt@c0 { compatible = "aspeed,ast2400-ibt-bmc"; reg = <0xc0 0x18>; @@ -264,6 +271,7 @@ reg-shift = <2>; interrupts = <32>; clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>; + resets = <&lpc_reset 5>; no-loopback-test; status = "disabled"; }; @@ -274,6 +282,7 @@ reg-shift = <2>; interrupts = <33>; clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>; + resets = <&lpc_reset 6>; no-loopback-test; status = "disabled"; }; @@ -284,6 +293,7 @@ reg-shift = <2>; interrupts = <34>; clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>; + resets = <&lpc_reset 7>; no-loopback-test; status = "disabled"; }; |