diff options
| author | Kishon Vijay Abraham I <kishon@ti.com> | 2018-04-27 17:39:04 +0530 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2018-05-03 10:32:19 -0700 |
| commit | c29fd489118a2abd2d17c49ae980e3c67fa6d004 (patch) | |
| tree | f67bbbdf7653c36a4f7df2eea27179f9e9dda156 /arch/arm/boot/dts/dra7.dtsi | |
| parent | 940293affa7ed7c0bdb1820ecf7a8f12e901d030 (diff) | |
ARM: dts: dra7: Add high speed modes capability to MMC1/MMC2 dt node
While the supported UHS mode can be obtained from CAPA2
register, SD Host Controller Standard Specification
doesn't define bits for MMC's HS200 and DDR mode capability.
Add properties to indicate MMC HS200 and DDR speed mode capability in
dt node.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/dra7.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/dra7.dtsi | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi index ae2f8dd46328..9dcd14edc202 100644 --- a/arch/arm/boot/dts/dra7.dtsi +++ b/arch/arm/boot/dts/dra7.dtsi @@ -1086,6 +1086,8 @@ status = "disabled"; pbias-supply = <&pbias_mmc_reg>; max-frequency = <192000000>; + mmc-ddr-1_8v; + mmc-ddr-3_3v; }; hdqw1w: 1w@480b2000 { @@ -1104,6 +1106,9 @@ max-frequency = <192000000>; /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */ sdhci-caps-mask = <0x7 0x0>; + mmc-hs200-1_8v; + mmc-ddr-1_8v; + mmc-ddr-3_3v; }; mmc3: mmc@480ad000 { |