diff options
| author | Philippe Schenker <philippe.schenker@toradex.com> | 2019-01-31 15:30:29 +0100 |
|---|---|---|
| committer | Oleksandr Suvorov <oleksandr.suvorov@toradex.com> | 2021-01-27 20:36:38 +0200 |
| commit | 3943d2b42c36fbb65695a3b73355d451ca281fab (patch) | |
| tree | e66ff9498a3dbb5fcaea6685811f789f04607a8d /arch/arm/boot/dts/imx6qdl-apalis.dtsi | |
| parent | 9cefd46289a58baaaf1b93fa5e74f491824e6aac (diff) | |
ARM: dts: imx6: Add sleep state to can interfaces
This patch prepares the devicetree for the new Ixora V1.2 where we are
able to turn off the supply of the can transceiver. This implies to use
a sleep state on transmission pins in order to prevent backfeeding.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
(cherry picked from commit c1016f5da0dbb8291575949e7f4a417c6306d70a)
(cherry picked from commit 08469025b03342c1f22f1eaf53e74fbf6022b3a6)
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-apalis.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl-apalis.dtsi | 27 |
1 files changed, 21 insertions, 6 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index 7c4ad541c3f5..59ed2e4a1fd1 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -148,14 +148,16 @@ }; &can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_flexcan1_default>; + pinctrl-1 = <&pinctrl_flexcan1_sleep>; status = "disabled"; }; &can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_flexcan2_default>; + pinctrl-1 = <&pinctrl_flexcan2_sleep>; status = "disabled"; }; @@ -599,19 +601,32 @@ >; }; - pinctrl_flexcan1: flexcan1grp { + pinctrl_flexcan1_default: flexcan1defgrp { fsl,pins = < MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0 MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0 >; }; - pinctrl_flexcan2: flexcan2grp { + pinctrl_flexcan1_sleep: flexcan1slpgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x0 + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0 + >; + }; + + pinctrl_flexcan2_default: flexcan2defgrp { fsl,pins = < MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0 >; }; + pinctrl_flexcan2_sleep: flexcan2slpgrp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x0 + MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x0 + >; + }; pinctrl_gpio_bl_on: gpioblon { fsl,pins = < |