diff options
| author | Stefan Agner <stefan@agner.ch> | 2018-07-09 17:48:48 +0200 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2018-07-11 21:01:01 +0800 |
| commit | b074f057ac60d32f604e0ca3120064e688e9a622 (patch) | |
| tree | a9aae9f9893da49fbecc74a27d6a083feabb1b9b /arch/arm/boot/dts/imx6qdl-apalis.dtsi | |
| parent | 330f85598e87497974431c0f6f736e413ccf2d27 (diff) | |
ARM: dts: imx6qdl-apalis/-colibri: remove unused pinctrl groups
100/200MHz states for USDHC3 are not required since the SoC
does not support modes faster than DDR52 for the on board eMMC.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-apalis.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl-apalis.dtsi | 34 |
1 files changed, 0 insertions, 34 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index 8c04f42fdb71..05f07ea3e8c8 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -947,38 +947,4 @@ MX6QDL_PAD_SD3_RST__SD3_RESET 0x17059 >; }; - - pinctrl_usdhc3_100mhz: usdhc3100mhzgrp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 - /* eMMC reset */ - MX6QDL_PAD_SD3_RST__SD3_RESET 0x170b9 - >; - }; - - pinctrl_usdhc3_200mhz: usdhc3200mhzgrp { - fsl,pins = < - MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 - MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 - MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 - MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 - MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 - MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 - MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 - MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 - MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 - MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 - /* eMMC reset */ - MX6QDL_PAD_SD3_RST__SD3_RESET 0x170f9 - >; - }; }; |