diff options
| author | Fugang Duan <b38611@freescale.com> | 2014-09-09 14:53:13 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:06:03 +0800 |
| commit | 00355b6ccaa57956cdbe4088a6dc390a76886b7a (patch) | |
| tree | a8b7f7bb8d84a4cb46d9b32279269b881b5d8b97 /arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | |
| parent | b8dfe837841cfc6988400dfd32288da9f73af6d1 (diff) | |
MLK-11457-04 ARM: dts: imx6qdl: add uart3 pad set for sabreauto board
Add imx6qdl-sabreauto board uart3 DTE pad set. To avoid a flood of
dts files, there comment out DTE pinctrl set. If user want to test
DTE mode, it needs to rebuild the DTB file.
Signed-off-by: Fugang Duan <B38611@freescale.com>
(cherry picked from commit dc6028b08c6bd718d57866a1714f3977ba7820d3)
Signed-off-by: Arulpandiyan Vadivel <arulpandiyan_vadivel@mentor.com>
Signed-off-by: Srikanth Krishnakar <Srikanth_Krishnakar@mentor.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6qdl-sabreauto.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index 57b84e885dc6..824734bf0c1e 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -671,6 +671,24 @@ >; }; + pinctrl_uart3_1: uart3grp-1 { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 + >; + }; + + pinctrl_uart3dte_1: uart3dtegrp-1 { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_SD4_CMD__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1b0b1 + >; + }; + pinctrl_uart4: uart4grp { fsl,pins = < MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 @@ -832,6 +850,18 @@ status = "okay"; }; +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_1>; + pinctrl-assert-gpios = <&max7310_b 4 GPIO_ACTIVE_HIGH>, /* CTS */ + <&max7310_c 3 GPIO_ACTIVE_HIGH>; /* RXD and TXD */ + fsl,uart-has-rtscts; + status = "okay"; + /* for DTE mode, add below change */ + /* fsl,dte-mode; */ + /* pinctrl-0 = <&pinctrl_uart3dte_1>; */ +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart4>; |