diff options
| author | Robby Cai <robby.cai@nxp.com> | 2019-08-24 17:24:37 -0400 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:06:54 +0800 |
| commit | b6279d749dc19b423640210ac3972be4abe1c143 (patch) | |
| tree | b4eb84f16c45984c42c497f4344e382c278938b7 /arch/arm/boot/dts/imx6sll-evk.dts | |
| parent | 363e1f765bab3a8215d9d1d329bb0a7387cd6aa8 (diff) | |
arm: dts: imx6sll-evk: enable epdc and pxp on evk board
enable epdc and pxp on imx6sll-evk board
Signed-off-by: Robby Cai <robby.cai@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6sll-evk.dts')
| -rw-r--r-- | arch/arm/boot/dts/imx6sll-evk.dts | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts index 38497e14ded4..1604de71932b 100644 --- a/arch/arm/boot/dts/imx6sll-evk.dts +++ b/arch/arm/boot/dts/imx6sll-evk.dts @@ -147,6 +147,15 @@ soc-supply = <&sw1c_reg>; }; +&epdc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_epdc0>; + V3P3-supply = <&V3P3_reg>; + VCOM-supply = <&VCOM_reg>; + DISPLAY-supply = <&DISPLAY_reg>; + status = "okay"; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -343,6 +352,10 @@ status = "okay"; }; +&pxp { + status = "okay"; +}; + ®_3p0 { vin-supply = <&sw2_reg>; }; @@ -422,6 +435,36 @@ }; &iomuxc { + pinctrl_epdc0: epdcgrp0 { + fsl,pins = < + MX6SLL_PAD_EPDC_DATA00__EPDC_DATA00 0x100b1 + MX6SLL_PAD_EPDC_DATA01__EPDC_DATA01 0x100b1 + MX6SLL_PAD_EPDC_DATA02__EPDC_DATA02 0x100b1 + MX6SLL_PAD_EPDC_DATA03__EPDC_DATA03 0x100b1 + MX6SLL_PAD_EPDC_DATA04__EPDC_DATA04 0x100b1 + MX6SLL_PAD_EPDC_DATA05__EPDC_DATA05 0x100b1 + MX6SLL_PAD_EPDC_DATA06__EPDC_DATA06 0x100b1 + MX6SLL_PAD_EPDC_DATA07__EPDC_DATA07 0x100b1 + MX6SLL_PAD_EPDC_DATA08__EPDC_DATA08 0x100b1 + MX6SLL_PAD_EPDC_DATA09__EPDC_DATA09 0x100b1 + MX6SLL_PAD_EPDC_DATA10__EPDC_DATA10 0x100b1 + MX6SLL_PAD_EPDC_DATA11__EPDC_DATA11 0x100b1 + MX6SLL_PAD_EPDC_DATA12__EPDC_DATA12 0x100b1 + MX6SLL_PAD_EPDC_DATA13__EPDC_DATA13 0x100b1 + MX6SLL_PAD_EPDC_DATA14__EPDC_DATA14 0x100b1 + MX6SLL_PAD_EPDC_DATA15__EPDC_DATA15 0x100b1 + MX6SLL_PAD_EPDC_SDCLK__EPDC_SDCLK_P 0x100b1 + MX6SLL_PAD_EPDC_SDLE__EPDC_SDLE 0x100b1 + MX6SLL_PAD_EPDC_SDOE__EPDC_SDOE 0x100b1 + MX6SLL_PAD_EPDC_SDSHR__EPDC_SDSHR 0x100b1 + MX6SLL_PAD_EPDC_SDCE0__EPDC_SDCE0 0x100b1 + MX6SLL_PAD_EPDC_GDCLK__EPDC_GDCLK 0x100b1 + MX6SLL_PAD_EPDC_GDOE__EPDC_GDOE 0x100b1 + MX6SLL_PAD_EPDC_GDRL__EPDC_GDRL 0x100b1 + MX6SLL_PAD_EPDC_GDSP__EPDC_GDSP 0x100b1 + >; + }; + pinctrl_max17135: max17135grp-1 { fsl,pins = < MX6SLL_PAD_EPDC_PWR_STAT__GPIO2_IO13 0x80000000 /* pwrgood */ |