diff options
| author | Denys Drozdov <denys.drozdov@toradex.com> | 2022-01-18 12:10:35 +0200 |
|---|---|---|
| committer | Denys Drozdov <denys.drozdov@toradex.com> | 2022-01-26 10:32:31 +0200 |
| commit | 257578a333235fe04414699cbe9120598e12e363 (patch) | |
| tree | e5ed5d074107d1c60bb12c2f7064a4b30b30b736 /arch/arm/boot/dts/imx6ull-colibri.dtsi | |
| parent | 847ab1285694b409fb9fe645fb9ad2856d973eac (diff) | |
arm: dts: colibri-imx6ull: clean-up sd card dts
Keep +3.3V pull-ups interface by default in imx6ull-colibri.dtsi
SD card interface setting per board device tree:
imx6ull-colibri-aster.dtsi +3.3V pull-ups
imx6ull-colibri-eval-v3.dtsi +3.3V pull-ups
imx6ull-colibri-iris.dtsi +3.3V pull-ups
imx6ull-colibri-iris-v2.dtsi +1.8V signaling, UHS capable
Signed-off-by: Denys Drozdov <denys.drozdov@toradex.com>
Diffstat (limited to 'arch/arm/boot/dts/imx6ull-colibri.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6ull-colibri.dtsi | 19 |
1 files changed, 12 insertions, 7 deletions
diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index e5edf740f5c7..220b1aace0ba 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -270,9 +270,20 @@ }; &usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; + pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_cd>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz &pinctrl_snvs_usdhc1_cd>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz &pinctrl_snvs_usdhc1_cd>; + pinctrl-3 = <&pinctrl_usdhc1 &pinctrl_snvs_usdhc1_sleep_cd>; assigned-clocks = <&clks IMX6UL_CLK_USDHC1_SEL>, <&clks IMX6UL_CLK_USDHC1>; assigned-clock-parents = <&clks IMX6UL_CLK_PLL2_PFD2>; assigned-clock-rates = <0>, <198000000>; + bus-width = <4>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + keep-power-in-suspend; + no-1-8-v; + vqmmc-supply = <®_sd1_vqmmc>; + wakeup-source; }; &wdog1 { @@ -664,13 +675,7 @@ >; }; - pinctrl_snvs_usdhc1_cd_sleep: snvs-usdhc1-cd-slp-grp { - fsl,pins = < - MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0 - >; - }; - - pinctrl_snvs_usdhc1_sleep_cd: snvs-usdhc1-cd-grp-slp { + pinctrl_snvs_usdhc1_sleep_cd: snvs-usdhc1-cd-slp-grp { fsl,pins = < MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0 >; |