diff options
| author | Richard Zhu <hongxing.zhu@nxp.com> | 2020-05-13 10:29:50 +0800 |
|---|---|---|
| committer | Richard Zhu <hongxing.zhu@nxp.com> | 2020-06-11 10:06:32 +0800 |
| commit | 659c69d1a7e38dcfc858ec33709a7815bdb917be (patch) | |
| tree | a42f4c438db946eef26141a4badafa42bd056168 /arch/arm/boot/dts/imx7d.dtsi | |
| parent | 808c4bb81eddcd98445739b40fb800887cd1752e (diff) | |
MLK-24012-09 arm: dts: add imx7d pcie ep support
Add the iMX7D PCIe EP mode, and verify the EP mode on SDB board.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx7d.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx7d.dtsi | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index b620366fb01c..435100a25aa0 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -387,6 +387,32 @@ status = "disabled"; }; + pcie_ep: pcie_ep@33800000 { + compatible = "fsl,imx7d-pcie-ep"; + reg = <0x33800000 0x4000>, <0x40000000 0x10000000>; + reg-names = "regs", "addr_space"; + num-lanes = <1>; + clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>, + <&clks IMX7D_PCIE_PHY_ROOT_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy"; + assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>, + <&clks IMX7D_PCIE_PHY_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + + fsl,max-link-speed = <2>; + power-domains = <&pgc_pcie_phy>; + resets = <&src IMX7_RESET_PCIEPHY>, + <&src IMX7_RESET_PCIE_CTRL_APPS_EN>, + <&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>; + reset-names = "pciephy", "apps", "turnoff"; + fsl,imx7d-pcie-phy = <&pcie_phy>; + num-ib-windows = <4>; + num-ob-windows = <4>; + status = "disabled"; + }; + rpmsg: rpmsg{ compatible = "fsl,imx7d-rpmsg"; /* up to now, the following channels are used in imx rpmsg |