diff options
| author | Fugang Duan <fugang.duan@nxp.com> | 2019-08-12 14:48:10 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:05:50 +0800 |
| commit | f853942cf4fd9f31a86eb4d1380a4eb8050944db (patch) | |
| tree | 6e2d3b61abdaf086cd7f966691ee9852367809a4 /arch/arm/boot/dts/imx7s.dtsi | |
| parent | fa44d026c49644ac4ff3d75abb9eee6e24f2c719 (diff) | |
MLK-13910: ARM: dts: imx7d: correct enet clock CCGR register offset
Correct enet clock CCGR register offset.
CCGR6: IMX7D_ENET_AXI_ROOT_CLK (enet1 enet2 bus clocks)
CCGR112: IMX7D_ENET1_TIME_ROOT_CLK, IMX7D_ENET1_IPG_ROOT_CLK
CCGR113: IMX7D_ENET2_TIME_ROOT_CLK, IMX7D_ENET2_IPG_ROOT_CLK
IMX7D_ENET_PHY_REF_ROOT_DIV supply clock for PHY, no gate after the clock, its parent
clcok root has gate.
IMX7D_ENET1_REF_ROOT_DIV/IMX7D_ENET2_REF_ROOT_DIV supply clocks for enet IPG_CLK_RMII,
no gate after the clock, its parent clock root has gate.
IMX7D_PLL_ENET_MAIN_125M_CLK (anatop pll) supply clock for enet RGMII tx_clk.
Update copyright information.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx7s.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx7s.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index f265fd08fd1b..533437faa95d 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -1188,7 +1188,7 @@ <&clks IMX7D_ENET_AXI_ROOT_CLK>, <&clks IMX7D_ENET1_TIME_ROOT_CLK>, <&clks IMX7D_PLL_ENET_MAIN_125M_CLK>, - <&clks IMX7D_ENET_PHY_REF_ROOT_CLK>; + <&clks IMX7D_ENET_PHY_REF_ROOT_DIV>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; fsl,num-tx-queues = <3>; |