diff options
| author | Peter Chen <peter.chen@nxp.com> | 2019-06-24 10:02:57 +0800 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2019-06-24 23:12:18 +0800 |
| commit | 48cbd9ff53b7391111e8460c3d9307ba14a5f8c0 (patch) | |
| tree | 61fb0c2400eb57f02809344a046605a4e0b715b8 /arch/arm/boot/dts/imx7ulp-evk.dts | |
| parent | 5b7bd456318a700298dc9aa31e09dd295e6edc4a (diff) | |
ARM: dts: imx7ulp-evk: enable USBOTG1 support
Enable USBOTG1 support for evk board, it is dual-role function
port.
Signed-off-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx7ulp-evk.dts')
| -rw-r--r-- | arch/arm/boot/dts/imx7ulp-evk.dts | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx7ulp-evk.dts b/arch/arm/boot/dts/imx7ulp-evk.dts index 59f094ea591a..4245b33bb451 100644 --- a/arch/arm/boot/dts/imx7ulp-evk.dts +++ b/arch/arm/boot/dts/imx7ulp-evk.dts @@ -30,6 +30,17 @@ status = "okay"; }; + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_vbus>; + regulator-name = "usb_otg1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio_ptc 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + reg_vsd_3v3: regulator-vsd-3v3 { compatible = "regulator-fixed"; regulator-name = "VSD_3V3"; @@ -54,6 +65,17 @@ status = "okay"; }; +&usbotg1 { + vbus-supply = <®_usb_otg1_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1_id>; + srp-disable; + hnp-disable; + adp-disable; + over-current-active-low; + status = "okay"; +}; + &usdhc0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc0>; @@ -77,6 +99,19 @@ >; }; + pinctrl_usbotg1_vbus: otg1vbusgrp { + fsl,pins = < + IMX7ULP_PAD_PTC0__PTC0 0x20000 + >; + }; + + pinctrl_usbotg1_id: otg1idgrp { + fsl,pins = < + IMX7ULP_PAD_PTC13__USB0_ID 0x10003 + IMX7ULP_PAD_PTC16__USB1_OC2 0x10003 + >; + }; + pinctrl_usdhc0: usdhc0grp { fsl,pins = < IMX7ULP_PAD_PTD1__SDHC0_CMD 0x43 |