diff options
| author | Anson Huang <Anson.Huang@nxp.com> | 2019-08-08 08:08:30 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:05:43 +0800 |
| commit | 3535a94ea895e95a9cea35f85d57bf9fc8ccbbd0 (patch) | |
| tree | 159e07220fb7a74cb8a9af6865c83c2c28afc630 /arch/arm/boot/dts/imx7ulp.dtsi | |
| parent | 625e5c3e567264f23a0364c92e1d23d18d50b43a (diff) | |
ARM: dts: imx7ulp: Add OPP table for cpu0
Add OPP table for cpu0 to support i.MX7ULP cpufreq.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx7ulp.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx7ulp.dtsi | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi index c10b0ea6cec1..d8ba0f1b9577 100644 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -41,6 +41,23 @@ compatible = "arm,cortex-a7"; device_type = "cpu"; reg = <0>; + operating-points = < + /* KHz uV */ + 720000 1125000 + 500210 1025000 + >; + clocks = <&smc1 IMX7ULP_CLK_ARM>, + <&scg1 IMX7ULP_CLK_CORE_DIV>, + <&scg1 IMX7ULP_CLK_SYS_SEL>, + <&scg1 IMX7ULP_CLK_HSRUN_SYS_SEL>, + <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>, + <&scg1 IMX7ULP_CLK_SPLL_PFD0>, + <&scg1 IMX7ULP_CLK_SPLL_SEL>, + <&scg1 IMX7ULP_CLK_FIRC>, + <&scg1 IMX7ULP_CLK_SPLL>; + clock-names = "arm", "core_div", "sys_sel", "hsrun_sys_sel", + "hsrun_core", "spll_pfd0", "spll_sel", "firc", + "spll"; }; }; |