diff options
| author | Fugang Duan <fugang.duan@nxp.com> | 2019-07-22 10:20:31 +0800 |
|---|---|---|
| committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:04:47 +0800 |
| commit | 996554bb192859ed9a5bef6458bdb223ac7944c3 (patch) | |
| tree | dc740196a6b7920ad81a4fedb4ba77757d9cc60b /arch/arm/boot/dts/imx7ulp.dtsi | |
| parent | 0a6ce670127d682beefe58d3837c911ade018cf7 (diff) | |
ARM: dts: imx7ulp-evk: enable lpuart and edma
Enable lpuart and edma.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx7ulp.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx7ulp.dtsi | 39 |
1 files changed, 36 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi index cd2740227761..9e3b7a78b458 100644 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -178,8 +178,10 @@ clocks = <&pcc2 IMX7ULP_CLK_LPUART5>; clock-names = "ipg"; assigned-clocks = <&pcc2 IMX7ULP_CLK_LPUART5>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; assigned-clock-rates = <48000000>; + dmas = <&edma0 0 20>, <&edma0 0 19>; + dma-names = "tx","rx"; status = "disabled"; }; @@ -334,6 +336,33 @@ reg = <0x40800000 0x800000>; ranges; + edma0: dma-controller@40080000 { + #dma-cells = <2>; + compatible = "nxp,imx7ulp-edma"; + reg = <0x40080000 0x2000>, + <0x40210000 0x1000>; + dma-channels = <32>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "dma", "dmamux0"; + clocks = <&pcc2 IMX7ULP_CLK_DMA1>, <&pcc2 IMX7ULP_CLK_DMA_MUX1>; + }; + lpi2c6: i2c@40a40000 { compatible = "fsl,imx7ulp-lpi2c"; reg = <0x40a40000 0x10000>; @@ -365,8 +394,10 @@ clocks = <&pcc3 IMX7ULP_CLK_LPUART6>; clock-names = "ipg"; assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART6>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; assigned-clock-rates = <48000000>; + dmas = <&edma0 0 22>, <&edma0 0 21>; + dma-names = "tx","rx"; status = "disabled"; }; @@ -377,8 +408,10 @@ clocks = <&pcc3 IMX7ULP_CLK_LPUART7>; clock-names = "ipg"; assigned-clocks = <&pcc3 IMX7ULP_CLK_LPUART7>; - assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; assigned-clock-rates = <48000000>; + dmas = <&edma0 0 24>, <&edma0 0 23>; + dma-names = "tx","rx"; status = "disabled"; }; |