diff options
author | Fancy Fang <chen.fang@nxp.com> | 2019-08-22 19:55:21 +0800 |
---|---|---|
committer | Dong Aisheng <aisheng.dong@nxp.com> | 2019-11-25 16:06:50 +0800 |
commit | 9b20d36c1d815c8a443d3a2e3378fc01084360f1 (patch) | |
tree | 10af7e04b016f93dd728e39eaf99d51830bb32a4 /arch/arm/boot/dts/imx7ulp.dtsi | |
parent | c9978b4ac93fa17e6555e7381366f103b877d059 (diff) |
ARM: dts: imx7ulp: remove mipi pll clock node
According to the IMX7ULP reference manual, the mipi pll
clock comes from the MIPI PHY PLL output. So it should
not be defined as a fixed clock. So remove this clock
node and all the references to it.
Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Diffstat (limited to 'arch/arm/boot/dts/imx7ulp.dtsi')
-rw-r--r-- | arch/arm/boot/dts/imx7ulp.dtsi | 17 |
1 files changed, 4 insertions, 13 deletions
diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi index da0658ae5e24..be276e71fb69 100644 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -104,13 +104,6 @@ #clock-cells = <0>; }; - mpll: clock-mpll { - compatible = "fixed-clock"; - clock-frequency = <480000000>; - clock-output-names = "mpll"; - #clock-cells = <0>; - }; - sram: sram@20000000 { compatible = "fsl,lpm-sram"; reg = <0x1fffc000 0x4000>; @@ -359,9 +352,9 @@ compatible = "fsl,imx7ulp-scg1"; reg = <0x403e0000 0x10000>; clocks = <&rosc>, <&sosc>, <&sirc>, - <&firc>, <&upll>, <&mpll>; + <&firc>, <&upll>; clock-names = "rosc", "sosc", "sirc", - "firc", "upll", "mpll"; + "firc", "upll"; #clock-cells = <1>; }; @@ -402,13 +395,12 @@ <&scg1 IMX7ULP_CLK_APLL_PFD0>, <&scg1 IMX7ULP_CLK_UPLL>, <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, - <&scg1 IMX7ULP_CLK_MIPI_PLL>, <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, <&scg1 IMX7ULP_CLK_ROSC>, <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", - "upll", "sosc_bus_clk", "mpll", + "upll", "sosc_bus_clk", "firc_bus_clk", "rosc", "spll_bus_clk"; assigned-clocks = <&pcc2 IMX7ULP_CLK_LPTPM5>; assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>; @@ -440,13 +432,12 @@ <&scg1 IMX7ULP_CLK_APLL_PFD0>, <&scg1 IMX7ULP_CLK_UPLL>, <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>, - <&scg1 IMX7ULP_CLK_MIPI_PLL>, <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>, <&scg1 IMX7ULP_CLK_ROSC>, <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>; clock-names = "nic1_bus_clk", "nic1_clk", "ddr_clk", "apll_pfd2", "apll_pfd1", "apll_pfd0", - "upll", "sosc_bus_clk", "mpll", + "upll", "sosc_bus_clk", "firc_bus_clk", "rosc", "spll_bus_clk"; }; }; |