diff options
| author | Tony Lindgren <tony@atomide.com> | 2017-08-30 08:19:41 -0700 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2017-09-19 10:23:29 -0700 |
| commit | 514b2da46fcc10bd5f42446b9fa746ba2c80aaf1 (patch) | |
| tree | 1199c97f668d8003867b3fc5e4b00bec2187fcdf /arch/arm/boot/dts/omap4.dtsi | |
| parent | 370ad6b4670adfc3c5c7d5aad63347e8db839762 (diff) | |
ARM: dts: Add missing smartreflex node and binding for omap4
We are missing smartreflex device tree nodes for omap4 with
their related "ti,hwmods" properties that the SoC interconnect
code needs.
Note that this will only show up as a bug with "doesn't have
mpu register target base" boot errors when the legacy platform
data is removed.
And since we're missing the device tree binding for smartreflex,
let's also add it and document the existing omap3 use too.
Note that the related driver also needs to be updated to probe
using device tree and get the platform data passed to it using
auxdata with arch/arm/mach-omap2/pdata-quirks.c.
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Cc: Tero Kristo <t-kristo@ti.com>
Acked-by: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/omap4.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/omap4.dtsi | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi index 24a3f70f1eef..c48b7e8713ca 100644 --- a/arch/arm/boot/dts/omap4.dtsi +++ b/arch/arm/boot/dts/omap4.dtsi @@ -442,6 +442,27 @@ clock-frequency = <48000000>; }; + smartreflex_iva: smartreflex@4a0db000 { + compatible = "ti,omap4-smartreflex-iva"; + reg = <0x4a0db000 0x80>; + interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "smartreflex_iva"; + }; + + smartreflex_core: smartreflex@4a0dd000 { + compatible = "ti,omap4-smartreflex-core"; + reg = <0x4a0dd000 0x80>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "smartreflex_core"; + }; + + smartreflex_mpu: smartreflex@4a0d9000 { + compatible = "ti,omap4-smartreflex-mpu"; + reg = <0x4a0d9000 0x80>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + ti,hwmods = "smartreflex_mpu"; + }; + hwspinlock: spinlock@4a0f6000 { compatible = "ti,omap4-hwspinlock"; reg = <0x4a0f6000 0x1000>; |