diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-10-12 11:35:07 +0200 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2017-10-16 11:37:10 +0200 |
| commit | a60ddf507dda0ede43b72d348283d8725a5a83c7 (patch) | |
| tree | 72b4be2d80fc0e9a0125ab1c6e42b6d7b7809ca8 /arch/arm/boot/dts/r8a7743.dtsi | |
| parent | a7869a5bc82682ac31452e178b4b3e9f8b48e7df (diff) | |
ARM: dts: r8a7743: Add missing clock for secondary CA15 CPU core
Currently only the primary CPU in the CA15 cluster has a clocks
property, while the secondary CPU core is driven by the same clock.
Add the missing clocks property to fix this.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Chris Paterson <chris.paterson2@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7743.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7743.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index f29f15d4d659..4db4f61be25a 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -63,6 +63,7 @@ compatible = "arm,cortex-a15"; reg = <1>; clock-frequency = <1500000000>; + clocks = <&cpg CPG_CORE R8A7743_CLK_Z>; power-domains = <&sysc R8A7743_PD_CA15_CPU1>; next-level-cache = <&L2_CA15>; }; |